Ming-Ji Dai

Thermal conductivity of Si/SiGe superlattice films

We have evaluated the thermal conductivity of Si/SiGe superlattice films by theoretical analysis and experiment. In experiments, the ultrahigh vacuum chemical vapor deposition is employed to form the Si/Si0.71Ge0.29 and Si/Si0.8Ge0.2 superlattice films. The cross-plane thermal conductivities of these superlattice films are measured based on the 3ω method. In the theoretical analysis, the phonon transport in Si/Si1−xGex superlattice film is explored by solving the phonon Boltzmann transport equation. The dependence of the thermal conductivity of the Si/Si1−xGex superlattice films on the superlattice period, the ratio of layer thicknesses, and the interface roughness is of interest. The calculations show that when the layer thickness is on the order of one percentage of the mean free path or even thinner, the phonons encounter few intrinsic scatterings and consequently concentrate in the directions having high transmissivities. Nonlinear temperature distributions are observed near the interfaces, arising fr...

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chips back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

High efficiency silicon-based high power LED package integrated with micro- thermoelectric device

A new thermal management application of silicon-based thermoelectric (TE) cooler integrated with high power light emitting diode (LED) is investigated in present study. The silicon-based TE cooler herein is fabricated by MEMS fabrication technology and flip-chip assembly process that is used for high power LED cooling. An electrical-thermal conversion method is used to estimate the junction temperature of LED. Moreover, the integrating sphere is also used to measure the light efficiency of LED. The thermal images photographed by infrared camera demonstrated the cooling function of the silicon-based TE devices. The results also show that high power LED integrated with silicon-based thermoelectric cooler package can effectively reduce the thermal resistance to zero. In addition, the light efficiency of the LED (1 W) will increase under low TE cooler input power (0.55 W), which is about 1.3 times of that without TE cooler packaging.

Characteristics of Thermal Resistance for High Power LEDs

In this paper the accurate and fast measurement equipment was developed and applied to study the thermal characteristics of high power LEDs. The forward-voltage based method was conducted to measure the junction temperature of high power LEDs. Conduction type method is adopted to measure the temperature sensitivity parameter (TSP) with small magnitude of error compared with the traditional method. The experiment time was reduced from 3~4 hours to 10 minutes for one sample. It was demonstrated that the repeatability of the measurement system was well after the repeatability test. LEDs used here were 5 W single chip LED and 50 W multi-chip LED with 36 chips inside the LED. Thermal resistance of junction-to-case as function of input power and case temperature was discussed. It was shown that the 5 W LED revealed an increasing trend of thermal resistance with the input power at each case temperature but the contrary trend of 5OW LED. The results also exhibited the dependency of thermal resistance and case temperature. With the increasing case temperature, the value of thermal resistance became higher under each input power. Three factors affected the thermal performance including: the first, the relation between light output efficiency and junction temperature; the second, the effect of internal series electrical resistance Rin and external electrical resistance Rex; and the third, the materials degeneration of each part inside the LEDs package as the junction temperature increased. To combine the three factors could explain the thermal characteristics of high power LEDs.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration

In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

Through-Silicon Hole Interposers for 3-D IC Integration

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.

Evaluation of Temperature-Dependent Effective Material Properties and Performance of a Thermoelectric Module

We devised a novel method to evaluate the temperature-dependent effective properties of a thermoelectric module (TEM): Seebeck coefficient (Sm), internal electrical resistance (Rm), and thermal conductance (Km). After calculation, the effective properties of the module are converted to the average material properties of a p–n thermoelectric pillar pair inside the module: Seebeck coefficient (STE), electrical resistivity (ρTE), and thermal conductivity (kTE). For a commercial thermoelectric module (Altec 1091) chosen to verify the novel method, the measured STE has a maximum value at bath temperature of 110°C; ρTE shows a positive linear trend dependent on the bath temperature, and kTE increases slightly with increasing bath temperature. The results show the method to have satisfactory measurement performance in terms of practicability and reliability; the data for tests near 23°C agree with published values.