Sheng-Tsai Wu

Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO2, the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Through-Silicon Hole Interposers for 3-D IC Integration

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.

Evaluation of Temperature-Dependent Effective Material Properties and Performance of a Thermoelectric Module

We devised a novel method to evaluate the temperature-dependent effective properties of a thermoelectric module (TEM): Seebeck coefficient (Sm), internal electrical resistance (Rm), and thermal conductance (Km). After calculation, the effective properties of the module are converted to the average material properties of a p–n thermoelectric pillar pair inside the module: Seebeck coefficient (STE), electrical resistivity (ρTE), and thermal conductivity (kTE). For a commercial thermoelectric module (Altec 1091) chosen to verify the novel method, the measured STE has a maximum value at bath temperature of 110°C; ρTE shows a positive linear trend dependent on the bath temperature, and kTE increases slightly with increasing bath temperature. The results show the method to have satisfactory measurement performance in terms of practicability and reliability; the data for tests near 23°C agree with published values.

Thermo-mechanical analysis of thermoelectric modules

The present paper studies the thermo-mechanical performance of thermoelectric modules by utilizing the Finite Element Analysis FEA simulation software ANSYS. A typical type TEG device with 32 pairs of legs was constructed. Three different thickness for the pads with 100um, 500um, and 1000um were given for investigating the geometry effect. The thermo-electric results got well confirmed compared with analytical solution. The maximum Von Mises stress occurs on the contact surface between top pad and top substrate due to the large CTE mismatch between the copper pad and the A1N substrate, especially in the higher temperature case. This stress might lead to module failure and reduce the reliability.

Interplay and influence of thermomechanical stress in copper-filled TSV interposers

In this paper we use finite element simulations to determine the influence of two key design parameters on the thermomechanical stress and the stress interplay in copper-filled TSV arrays. The two parameters are the vias pitch-to-diameter ratio and thickness-to-radius (aspect) ratio. Our analytical results has suggested that the in-plane stress interplay becomes insignificant when the TSV pitch is at least five times of the vias radius. This criterion will be numerically verified in this paper. This work also suggests that it would be inadequate to approximate the thermomechanical stress into a simplified 2D models even for a small H/D ratio (which resembles a think, 2D-like structure).

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1-18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating.

Nonlinear thermal stress analyses and design guidelines for through silicon vias (TSVs) in 3D IC integration

In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.

Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration.