Witold P. Maszara

Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates

Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.

Locally strained ultra-thin channel 25nm narrow FDSOI devices with metal gate and mesa isolation

Strained silicon devices offer very high carrier mobility. If we put them on an SOI substrate we also improve short-channel control and junction leakage. In this paper, we present a new approach to introducing strain in very thin silicon layers. NMOS and PMOS CV/I performance of 0.2 ps and 0.3 ps, respectively, is the highest reported. We analyze 3D geometrical effects on stress, mobility, and drive currents using the 3D process and device simulator, Taurus.

High performance 25 nm FDSOI devices with extremely thin silicon channel

We demonstrate 25 nm mid-gap metal gate fully-depleted silicon on insulator (FDSOI) devices with the highest reported drive current for a single-gate PMOS device (I/sub on/=789 /spl mu/A//spl mu/m and I/sub off/=27 nA//spl mu/m for V/sub gs/-V/sub t/=1.25 V). We observe electron and hole mobility degradation for very thin channels (/spl sim/7 nm). Devices show good hot carrier and gate dielectric reliability.

Manufacturability of 20-nm ultrathin body fully depleted SOI devices with FUSI metal gates

Ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) devices show great performance due to undoped channels and excellent electrostatic control. Very high drive currents and good off-state leakage, ideal subthreshold slope, and small drain-induced barrier lowering (DIBL) have been reported with devices as short as 20 nm. The ultrathin channel enables high device performance, but it imposes a new set of problems. The control of the silicon thickness has become the dominant source of device variations. Selective epitaxial growth has become a necessity to achieve high performance and reliable contacts to UTB FDSOI devices. This work discusses silicon thickness control, selective epitaxial growth, and the mid-gap gate module needed for fully depleted devices. Very good control of short channel effect is shown and drive current fluctuations are discussed.

Multiple Gate MOSFETs

Planar single-gate transistors have been recently demonstrated with reasonable performance at sub-20 nm of physical gate length. However, a need for high performance transistors with channels shorter than that, as expressed by 2005 ITRS goals, requires devices with more than one gate, which facilitates better control of electrostatic charge in the channel. Double- and triple-gate transistors with their process integration complexity will likely become a device of choice for the high performance logic circuits in second decade of the 21 st century. This paper will discuss various approaches to realization of those multi-gate fully depleted channel devices and their performance and process integration issues and layout design challenges for sub-20 nm gates. We also discuss issues related to designing circuits with multi-gate fin-based devices.

High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric

High performance sub-60 nm SOI CMOS transistors have been developed. An aggressively scaled, 1.2 nm thick, gate dielectric sandwich containing silicon nitride and dioxide layers allowed full control of boron penetration with manageable levels of gate leakage. Excellent values of I/sub dsat/ of 850 /spl mu/A//spl mu/m and 500 /spl mu/A//spl mu/m for NMOS and PMOS were respectively obtained at V/sub dd/=1.2 V and I/sub off/=100 nA//spl mu/m. The CV/I metric was 1.0 and 1.9 ps for NMOS and PMOS respectively.

Extending the life of N/O stack gate dielectric with gate electrode engineering

Nitride/oxynitride (N/O) stack gate dielectrics show significant leakage reduction and strong boron penetration resistance as compared to oxynitrides. The life of the N/O stack can be further extended by gate electrode engineering. With pre-doped poly-Si gates for both N- and P-MOS devices, poly-Si gate depletion can be minimized and inversion Tox can be reduced. Employment of NiSi can further reduce inversion Tox by minimizing gate dopant deactivation. In addition, a fully-silicided (FUSI) NiSi metal gate electrode totally eliminates poly-Si gate depletion and reduces the inversion Tox by 4-6A. Both FDSOI devices and strained Si devices with N/O stack and FUSI metal gate showed performance improvements and no degradation in gate dielectric reliability.