Ibrahim Ban

Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory

Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-µA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.

Floating Body Cell with Independently-Controlled Double Gates for High Density Memory

An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit better memory characteristics at a lower voltage than alternative FBC structures at comparable dimensions. Design, fabrication, operation, and scalability of IDG FBC devices are discussed

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond

A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX

A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and TIP implants are critical for achieving the balance between long retention time and large memory signal. For a minimum 3-muA sensing window, worst-case disturb retention of 25 ms is shown in scaled devices with 55 nm gate-length (LG) and 65 nm width (W). FBC scaling is predicted to be feasible at 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

Silicon on replacement insulator (SRI) floating body cell (FBC) memory

A 15-nm node floating body cell (FBC) memory was demonstrated utilizing silicon on replacement insulator (SRI) technology on bulk substrate. Highly selective SiGe etch and nano-scale anchors enabled the fabrication of silicon on thin replacement oxide of 12 nm. The memory characteristics show a memory signal of 7 µA and disturb retention time of 20 ms for a 51-nm gate length and 77-nm width device. This is the best FBC memory performance reported on bulk substrate.

A low power electro-optic polymer clad Mach-Zehnder modulator for high speed optical interconnects

Electro-optic (EO) polymer cladding modulators are an option for low-power high-speed optical interconnects on a silicon platform. EO polymers have inherently high switching speeds and have shown 40 Gb/s operation in EO polymer clad ring resonator modulators (RRM). In EO polymer clad RRM, the modulator’s area is small enough to be treated as a lumped capacitor; the capacitance is sufficiently low that the modulation speed is limited by the bandwidth of the resonator. A high Q resonator is needed for low voltage operation, but this can limit the speed and/or require precise control of the resonator’s wavelength, necessitating power consuming heaters to maintain optimal performance over a large temperature range. Mach Zehnder modulators (MZM), on the other hand, are not as sensitive to temperature fluctuations, but typically are relatively long and must employ power consuming terminated travelling wave electrodes. In this paper, a novel MZM design is presented using an EO polymer clad device. In this device, the electrodes are broken into short parallel segments and the waveguide folds around them. The segments of the electrode length are designed to provide good signal integrity up to 20 GHz without termination. The electrodes are driven by a single drive voltage and provide push-pull modulation. Modulators were designed and fabricated using silicon nitride waveguides on bulk silicon wafers and were demonstrated at high speed (20 GHz). A VπL as low as 1.7 Vcm is measured on initial devices. An optimized device could provide 40 Gb/s performance at 1 V drive voltages, ~100 fF total device capacitance and less than 2 dB optical insertion loss.

Efficient and scalable single mode waveguide coupling on silicon based substrates

One of the key challenges in Silicon based optical interconnect system remains to be the efficient coupling of optical signals from the submicron size on-chip waveguides to standard single mode (SM) fibers with low insertion loss (IL) and relaxed alignment tolerance. Large optical alignment tolerance allows optical connectors to be attached to on-chip waveguides passively using standard semiconductor pick-and-place assembly tools that have placement accuracies of 10- 15μm. To facilitate the assembly, optical fiber coupling elements need to be modular and compact. They have to also have low profile to avoid blocking air flow or mechanical interference with other elements of the package. In this paper we report the development of a two-dimensional (2D) SM optical fiber coupling architecture that consists of Si based photonic lightwave circuit (PLC) substrate and a high-density micro-lensed fiber optic connector. The system is compact, efficient and has large optical alignment tolerance. At 1300nm an insertion loss of 2.4dB and 1.5dB was measured for the PLC module and the fiber optic connector, respectively. When the PLC module and connector was aligned together, a total insertion loss of 7.8dB was demonstrated with x,y alignment tolerance of 40μm for 1dB optical loss. The SM optical coupling architecture presented here is scalable, alignment tolerant and has the potential to be manufactured in high volume. To our knowledge, such a system has not been reported in the literature so far.