Miroslaw Zoladz

A bidirectional 64-channel neurochip for recording and stimulation neural network activity

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DACs. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

Design and measurements of 64-channel ASIC for neural signal recording

This paper presents the design and measurements of a low noise multi-channel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and was fabricated in CMOS 0.18 µm technology. A single readout channel is built of an AC coupling circuit at the input, a low noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and matching performance with the possibility of cut-off frequencies tuning. The low cut-off frequency can be tuned in the 1 Hz–60 Hz range and the high cut-off frequency can be tuned in the 3.5 kHz–15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 µW the equivalent input noise is in the range from 6 µV–11 µV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency is on the same level. The chip occupies 5×2.3 mm2 of silicon area.

Design and measurements of low power multichannel chip for recording and stimulation of neural activity

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm2 of silicon area and consumes only 25 μW/channel. A low cut-off frequency can be tuned in the 60 mHz - 100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 μV rms in 100 Hz - 12 kHz band and 7.6 μV rms in 3 Hz - 12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA - 512 μA range.

PXD18k - fast single photon counting chip with energy window for hybrid pixel detector

We report on the design of an integrated circuit called PXD18k dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The PXD18k has dimensions of 9.64 mm × 20 mm and is designed in CMOS 180 nm technology. The core of the IC is a matrix of 96×192 pixels with 100 µm ×100 µm pixel size working in a single photon counting mode. Each pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent threshold A and B) and two 16-bit ripple counters. To minimize the effective threshold spread, one 7-bit and one 5-bit trim DACs are used in each pixel for correction of threshold A and threshold B respectively. The data are read out via 8 LVDS outputs with 100 Mbps rate. The power consumption is dominated by the analog blocks and it is about 23 µW/pixel. The effective peaking time at the discriminator input is 30 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 42.5 µV/e− and an Equivalent Noise Charge with bump-bonded detector is 168 e− rms. The effective threshold spread at the discriminator input is only 1.79 mV (at one sigma level, with 7-bit trim DACs enabled). The count rate per pixel depends on the effective CSA feedback resistance and for a standard setting a dead time of the front-end electronics is 172 ns (paralyzable model). The PXD18k IC works with two energy thresholds in the readout mode separate from exposure. When operating with two different energy thresholds, acquisition and readout are interleaved and the readout dead time is 740 µs. The PXD18k can also operate in a continuous readout mode with zero dead time and one can select the number of bits readout from each pixel to optimize the IC frame rate. For example for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises up to 7.1 kHz.

A complete 256-channel reconfigurable system for in vitro neurobiological experiments

We present a complete reconfigurable measurement system for 256-channel in vitro recordings and electrical stimulation of brain tissue electrophysiological activity. The system is built of: brain tissue life support system, Microelectrode Array (MEA), 4 multichannel integrated electronic circuits for signals conditioning and electrical stimulation, Digitizer and PC Application for measurement, data presentation and storage. The life support system is responsible for keeping brain tissue samples in appropriately saturated artificial cerebrospinal fluid at a very stable temperature. We designed two versions of the ASICs that can be easily adopted to the system. These are processed in the CMOS 180nm technology and differ with the main parameters that suits for different types of experiments. The ASICs are dedicated to amplification, filtering, and electrical stimulation of the 256 channels while the Digitizer performs simultaneous data acquisition from 256 channels with 14 kS/s sample rate and 12bit resolution. The resulting byte stream is transmitted to PC via USB (Universal Serial Bus). We also show a neurobiological experiment results that confirm the system is able to keep the extracted brain tissue active (posterior hypothalamic slices) and to record local theta field potentials with very small amplitudes from multiple neurons simultaneously.

Design of 64-channel analogue multiplexer for neural application in CMOS 180 nm technology

This paper presents the design and simulation of the 64 channel analogue multiplexer for neural signal recording system designed in CMOS 180 nm technology. Single channel sampling rate is 100 kHz and linear range of the input signal is +/-400 mV. For noise cancellation caused by digital part of the differential architecture with dummy channel has been used.

Effective noise minimization in multichannel recording circuits processed in modern technologies for neurobiology experiments

This paper presents an effective method of input referred noise minimization (IRN) of recording stages dedicated to neurobiology experiments and processed in submicron or nanometer technologies. We analyze different approaches for IRN minimization and propose solution based on the on-chip analogue noise averaging. The proposed approach allows for almost 2.5 times IRN minimization with only 8 time power consumption increase whereas other on-chip analogue methods provides much less noise minimization efficiency. The method is confirmed by measurements of 8-channel integrated circuit fabricated in 180nm commercial process. The chip is composed of the 8-recording channels that are individually digitally assisted for enlarging IC functionality. The recording part is divided into two separate channels, i.e. an Action Potential (AP) stage and a Local Field Potential (LFP) stage. The voltage gain of the AP and LFP stages can be switched between 56/50 dB and 50/45 dB respectively. Corner frequencies of a particular stages can be digitally controlled in a wide range, i.e. the upper cut-off frequency can be changed in the 20 Hz - 2 kHz (LFP stage) while the lower cut-off frequency can be tuned at the 120 mHz - 3 kHz (LFP and AP stage). The upper cut-off frequency of the AP stage is equal to 6.9 kHz. A single recording channel is supplied from ±0.9 V and consumes about 4.8 μW of power. For a default channel configuration the Input Referred Noise is equal to 5.6 μV resulting in 4.38 of Noise Efficiency Factor (NEF) while for on-chip averaging mode enabled the IRN can be limited to 2.4 μV resulting in 5.3 of NEF.

Main parameters uniformity enhancement in multichannel integrated circuits dedicated to biomedical signals recordings

This paper presents an approach for main parameters uniformity improvement from channel to channel in integrated circuit dedicated to multi-point neurobiological recordings. We show that if the conditioning channel size and power consumption are very limited, additional correction circuits are necessary to key parameters spread lowering. The method has been implemented in a 64-channel circuit fabricated in 180 nm CMOS technology and resulted in tenfold reduction of corner frequency spread (from 59% down to 4%) and fourfold reduction of DC offset (from 31.6% down to 7.5%). The correction circuit has also been used in a novel optimization method which allows for more than 30 dB Common Mode Rejection Ratio increase. It is also worth mentioning that the proposed methodology is very efficient and has minor impact on the overall channel size and power consumption A single recording channel consumes 8.5 μW of power and occupies 0.065 mm2 of silicon area while its Input Referred Noise is equal to 5μVRMS.

Design for the testability of the multichannel neural recording and stimulating integrated circuit

We report on design of the 100 channel integrated circuit (10×10 pixel matrix) destined to complex neurobiology experiments. The chip is dedicated to both recording and stimulating neural activity and its predominant attributes comes from its individual digital control of both blocks and allocation of both in each of the pixel. Additionally, the integrated circuit is composed of RAM, ADC, bandgap reference, programmable analog multiplexer and programmable biasing block. The chip is designed in CMOS 180mn process and occupies 5×5 mm2. The paper focuses on design of these type of chips in order to facilitate its tests. The main ICs blocks are described and its preliminary measurements are shown.

Design of a control system for ultrafast x-ray camera working in a single photon counting mode

Prototype of Ultra-Fast X-Ray Camera Controller working in a single photon counting mode and based on ASIC has been presented in this paper. An ASIC architecture has been discussed with special attention to digital part. We present the Custom Soft Processor as an ASIC control sequences generator. The Processor allows for dynamic program downloading and generating control sequences with up to 80MHz clock rate (preliminary results). Assembler with a very simple syntax has been defined to speed up Processor programs development. Discriminators threshold dispersion correction has been performed to confirm proper Camera Controller operation.