Mitsuaki Iwashita

Advanced ultraviolet cross-link process and materials for global planarization

The use of conventional thermal cross-link materials such as negative resists, antireflective coating, and planarizing layers does not lead to excellent planarization for multilevel interconnects and specially via arrays prior to trench patterning for an advance lithography. The large thicknesses bias between the blanket areas and interconnect areas, and between the blanket areas and via arrays are usually observed. Large thickness bias creates problems during next lithography by narrowing the process latitude. Recently, chemical mechanical polishing (CMP) technology has been proposed to achieve the planarization. However, CMP planarization technique is very sensitive to pattern density, and there is a strong possibility that chemical etching reaction will increase the dielectric constant. The current CMP technique still requires a new investment in the equipment. We report another novel approach for global planarization using UV cross-link material (XUV TM ) and the dielectric UV exposure unit in coater equipment (Clean Track). This planar technique provides benefits for reducing the thickness bias observed in the 22- to 65-nm generation lithography and imprint processes. Using this technique, XUV TM TNG076 has achieved global planarization of 10-nm thickness bias in 85-nm diameter via topography when the blanket film thickness was only 110 nm.

LWR reduction in low-k1 ArF-immersion lithography

Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches such as materials, exposure technology and the track process have been performed for LWR reduction during lithography process. It was reported that the post-development bake process had good performance for LWR reduction (1). However, the post-development bake process induced large CD change owing to the degradation of large isolated resist pattern. Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography. The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process, the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process. Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR in ArF immersion lithography.

LWR reduction in ArF resist pattern by resist smoothing process

With the scaling down of the semiconductor design rule, the requirement to reduce the roughness of the resist pattern used in lithography processing has become crucial. Two typical examples of resist-pattern roughness are line-edge roughness (LER) and line-width roughness (LWR). In particular, as the wavelength of the optical light source has been shortened from 248 nm (KrF source) to 193 nm (ArF source), the problem that LWR is produced with a scaled-down ArF resist pattern has become a cause of deterioration in device characteristics. And with further scaling down in the future, decreasing this LWR on the resist pattern will become a major challenge facing lithography processing. Accordingly, to meet this challenge, it has thus become urgent to find a good method for reducing LWR. At present, for LWR reduction during lithography processing, various measures have been tried and many studies taking different approaches-addressing materials (resist, etc.), exposure technology (mask, etc.), and the track process-have been performed. A decisive method of reducing LWR, however, has not yet been found. Aiming at reducing LWR, we have thus developed a process for treating the post-development resist pattern in an organic-solvent atmosphere. This resist smoothing process is effective method for both Krf resist and Arf resist, moreover it was achieved that VUV pre-treatment improve solvent solubility against resist, especially Arf resist. As a result, the LWR of a resist pattern after undergoing this treatment process was substantially decreased. Moreover, as for the roughness produced during the following etching process for forming the gate electrode, it was confirmed that the effect of decreasing LWR of the resist pattern is carried forward to this next process. In this paper, the developed LWR-reduction method for an ArF ultra-fine pattern is explained, and LWR reduction results achieved with method are presented.

Etch durable spin-on hard mask

As decreasing the device feature size, the film stack structure used in resist process is also changing. Especially multilayer stack film structure is getting popular for pattern formation on critical layers. Our approach is to form a spin-on hard mask film with high etch resistance by introduction of a new baking function. The results show that a spin-on hard mask film processed by an underlayer coating system of Tokyo Electron Ltd. (TEL) has drastically improved etch resistance compared to a conventional system. We will report the availability of new underlayer system using several kinds of underlayer materials.

Electro-less barrier/seed formation in high aspect ratio via

This paper reports on the results of applying an electroless (Eless) plating technique to the deposition of barrier and seed layers in high aspect ratio through-silicon vias (TSVs) and its potential for reducing costs, improving performance, and raising productivity in 3D Integration. The newly developed technology is applicable not only to barrier/seed deposition on TEOS insulation film but also to the uniform deposition of a seed layer on conventional vacuum-deposited barrier layers (such as PVD-Ta). The application of Eless technology can also reduce the occurrence of voids at the bottom of vias that easily occur in Cu electroplating, even when using thin-film seed layers (under 100 nm), which means that improved productivity and reduced process costs can also be expected.

Nanopatterning of diblock copolymer directed self-assembly lithography with wet development

We report wet development technique for directed self-assembly lithography pattern. For typical diblock copolymer, poly (styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by O2 plasma. However, O2 plasma attack also etches off PS area simultaneously. As a result, the thickness of residual PS pattern is thinner and it causes degradation of PS mask performance. PS thickness loss in the device integration is not desirable as etching mask role. In this work, we applied wet development technique which could be higher selectivity to keep PS film thickness after pattern formation. Especially, we propose the method using low pressure mercury lamp and conventional TMAH (2.38%) as developer. It is expected to accomplish pattern formation in one track with coating, baking, exposure and development.

Ultraviolet cross-link process using spin-coating materials for advanced planarization and sublimate defect reduction

This study focuses on ultraviolet cross-link process using spin-coating materials for advanced planarization and sublimate defect reduction in the advanced process techniques of semiconductor, display, and new electronic devises. The ultraviolet cross-link process and spin-coating material have been optimized and studied for excellent global planarization property. The newest approach by excellent collaborations from both process and material has the planarization property on an irregular substrate such as the patterned steps, holes and trenches to increase the depth of focus and pattering resolution. After planarizing the substrate surface, the ultraviolet planar materials are used to provide the dry or wet etching selectivities against the under-layer, and specially, avoid the dry or wet etching damage as an etch protecting layer. In addition, we reported the newest process using developed ultraviolet irradiation tool on in-line system in an coater equipment (TOKYO ELECTRON LTD CLEAN TRACKTM) for manufactability with higher throughput (Spin-coating time: less than 30 sec., ultraviolet irradiation time: less than 5 sec, low temperature baking time: less than 60 sec.) Using this technique, a remarkable reduction in via topography with 1.1 μm as a depth and 0.9-1.0 μm as a diameter has been achieved excellent thickness bias less than 20 nm. And, the sublimate amount of the film obtained from the developed ultraviolet planar material was very low as compared with that of the film obtained from current standard thermal cross-link material as the reference.

Novel approach of UV cross-link process for advanced planarization technology in 32-45 nm lithography

Conventional method of patterning trenches in a via first trench last Dual Damascene process involves filling the thickness bias with thermal cross-link gap fill material and then applying the photoresist followed by trench lithography. The major problem of this process is the large thickness bias (step height) observed as the via pattern pitch and density changes across the wafer. Now, the new approach of UV cross-link system instead of thermal cross-link gap fill material is proposed. The material is referred to as UV cross-link film (XUVTM). The main properties of UV cross-link film are small thickness bias of blanket field and dense-via pattern, high planarization, and void free by using the newest UV cross link process that we studied in UV-photo irradiation system. The process for UV cross-link film is very simple, just UV ray irradiate the film for about 10 s in the same coater-developer tool. In this paper, we study the novel approach, UV cross-link process for reducing the thickness bias. The planarization of XUVTM was very high as compared with that of the film obtained from thermal cross-link gap fill material as the reference. The application of UV cross- link process using XUVTM is one of the most promising processes ready to be investigated into mass production to leave out the dry etch back process before patterning trench in via first trench last Dual Damascene lithography.

Feasibility studies of coating method for planarization process

The lithography process on topographic substrate is one of the most critical issues for device manufacturing. Topographic substrate-induced focus variation occurs between top position and bottom position in a layer. That is, common depth of focus is reduced. This focus variation is sure to ruin the focus budget in low k1 lithography. From the focus budget of CMOS device, substrate topography is required to be less than 30nm for hp 45-nm generation devices and less than 15nm for hp 32-nm generation devices. In this paper, the authors evaluate a novel concept for hp45-nm generation dual damascene layer for global surface planarization. The novel concept is thin planarization layer with bottom anti-reflecting (BAR) function. This planarization layer with optical performance is materialized by UV crosslink materials and process. This concept is expected to lead to a simpler planarization process. Thin planarization layer with BAR function clear BARC layer and simplifies the etching process. Our study showed that the planarization performance of UV crosslink layer with 100nm thickness was 20nm thickness bias between the field area and dense via hole area. This thickness bias achieved the requirement of hp 45nm generation. Furthermore, fine resist pattern was resolved on the planarization layer by the optimization of acid components and additive.

Robust lithography application to prevent resist poisoning in BEOL

As feature sizes become increasingly smaller in integrated circuits, the occurrence of resist-pattern defects (resist poisoning) has become a serious problem in Back End Of Line (BEOL) Dual Damascene (DD) processing. Against this background, we have researched a bi-layer silylation process as one type of multi-layer process and evaluated its effectiveness as a countermeasure to resist poisoning. In the bi-layer silylation process, two layers of chemically amplified resist (CAR) are formed on novolac, and after wet-developing the upper CAR layer by an alkali developer, a silylation reaction is generated to make the resist pattern resistant to O2 reactive ion etching (RIE). We found that the bi-layer silylation process was an effective countermeasure to resist poisoning in a methylsilsesquioxane (MSQ) DD structure with a 160-nm via, and that a 160-nm MSQ DD structure could be formed. We also found that the occurrence of resist poisoning depended greatly on the surface conditions of the via structure and on the resist-ashing technique.