Mohamad M. Jahanbani

1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Metrology Of Silicide Contacts For Future CMOS

Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low‐resistance contacts between the back‐end (W plugs and Cu interconnects) and front‐end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid‐gap silicide, i.e., the Fermi level of the NiSi metal is pinned half‐way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source‐drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band‐edge silicides, such as PtSi for contacts to p‐type or rare earth silicides for contacts to n‐type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufac...

Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices

Characteristic Study of SOI eSiGe Techonology

This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.