Moshe E. Preil

Assessment of OPC effectiveness using two-dimensional metrics

A complete evaluation of the optical proximity effects (OPE) and of their corrections (OPC) requires a quantitative description of two-dimensional (2D) parameters, both at resist- and at reticle-level. Because the 2D behaviour at line-ends and at line-corners can become a limiting factor for the yield, it should be taken into account when characterising a process, just as the CD- and pitch-linearity are already kept under control. This implies the measurement of 2D-metrics in a precise way. We used an SEM Image Analysis tool (ProDATA SIAM) to define and measure various OPC-relevant metrics for a C013 process. For the METAL (M1) process, we show that the overlap between line-ends of M1-trenches and underlying nominal contacts is a relevant metric to describe the effectiveness of hammerheads. Moreover, it is an interesting metric to combine with the CD process window. For the GATE process, we demonstrate that for a given set of metrics there is a degree of OPC aggressiveness beyond which it is not worth to go. We considered both line-end shortening (LES) and corner rounding affecting the poly linewidth close to a contact pad, and this on various logic circuits having received different degrees of fragmentation. Finally the knowledge of the actual line-end contour on the reticle allows one to simulate separately the printing effect of that area loss at reticle line-ends. The area loss measured by comparing the extracted contour to the target one is regarded as a combination of pull-back and area loss at corners. For our C013 gate process, and for the 130nm lines at a 1:1.25 duty cycle, those two parameters contribute together to approximetely 40% of the measured LES in the resist. This fact raises the question of specifications on 2D reticle parameters. We also find a linear correlation between the area loss at reticle line-end corners and the corresponding increase of LES on the wafer, which suggests a way towards putting specifications on the reticle line-ends.

Characterization of optical proximity correction features

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designers intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designers intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

New approach to correlating overlay and yield

Integrated circuit design rules are defined with a given overlay tolerance, but the exact correlation between measured overlay on product wafers and die yield is notoriously difficult to quantify. Interest in better quantifying this relationship is not merely academic. The ability to shrink the overlay design rule by even a few nanometers would allow more good die to be printed on every product wafer, providing a substantial economic benefit. Conversely, if the actual distribution of overlay errors across a wafer is slightly worse than anticipated in the design rules, the resulting shortfall in yield would be difficult to identify and correct.

Sampling plan optimization for detection of lithography and etch CD process excursions

Effective sample planning requires a careful combination of statistical analysis and lithography engineering. In this paper, we present a complete sample planning methodology including baseline process characterization, determination of the dominant excursion mechanisms, and selection of sampling plans and control procedures to effectively detect the yield- limiting excursions with a minimum of added cost. We discuss the results of our novel method in identifying critical dimension (CD) process excursions and present several examples of poly gate Photo and Etch CD excursion signatures. Using these results in a Sample Planning model, we determine the optimal sample plan and statistical process control (SPC) chart metrics and limits for detecting these excursions. The key observations are that there are many different yield- limiting excursion signatures in photo and etch, and that a given photo excursion signature turns into a different excursion signature at etch with different yield and performance impact. In particular, field-to-field variance excursions are shown to have a significant impact on yield. We show how current sampling plan and monitoring schemes miss these excursions and suggest an improved procedure for effective detection of CD process excursions.

Measurement and analysis of reticle and wafer-level contributions to total CD variation

The impact of reticle critical dimension (CD) variations on wafer level CD performance has been growing with the trend towards sub-wavelength lithography. Reticle manufacturing, CD specifications and qualification procedures must now take into account the details of the wafer fab exposure and process conditions as well as the mask process. The entire pattern transfer procedure, from design to reticle to wafer to electrical results, must be viewed as a system engineering problem. In this paper we show how hardware and software tools, procedures, and analysis techniques are being developed to support the demanding requirements of the pattern transfer process in the era of 0.13 micron lithography.

Automated method for overlay sample plan optimization based on spatial variation modeling

In this paper, we present an automated method for selecting optimal overlay sampling plans based on a systematic evaluation of the spatial variation components of overlay errors, overlay prediction errors, sampling confidence, and yield loss due to inadequate sampling. Generalized nested ANOVA and clustering analysis are used to quantify the major components of overlay variations in terms of stepper-related systematic variances, systematic variances of residuals, and random variances at the wafer, field and site levels. Analysis programs have been developed to automatically evaluate various sampling plans with different number of fields and layouts, and identify the optimum plan for effective excursion detection and stepper/scanner control. For each sample plan, the overlay prediction error relative to full wafer sample is calculated, and its sampling confidence is estimated using robust tests. The relative yield loss risk due to inadequate sampling is quantified, and compared with the cost of sampling in determining a cost-optimal sampling plan. The methodology is applied to overlay data of CMP processed wafers. The different spatial variation characteristics of oxide and metal CMP processes are compared and proper sampling strategies are recommended. The robustness of the recommended sample plans was validated over time. The sample plan optimization program successfully detected process change while maintaining accurate and robust stepper/scanner control.

Factors that determine the optimum reduction factor for wafer steppers

The optimum reduction factor for stepper lenses is determined by trade-offs among several competing constraints and practical limitations. Lens reduction factor were chosen initially on the basis of several factors, including maximum lens element size, usable reticle field, stepper throughput and reticle glass size. These considerations led to the choice of 5x for the reduction factor initially and 4x for the most recent generation of step-and-scan systems. A large reduction factor is beneficial because it reduces the negative impacts of reticle linewidth variations, reticle registration errors, and reticle defects. This is particularly important for optical lithography processes that operate near the diffraction limit, where the mask error factor can be large. For this reason, as well travel down the roadmap, the 4x reduction factor for critical stepper lenses needs to be reconsidered. Before a decision is made, all consequences of a large reduction factor must be taken in to account. For fixed field sizes, reduction factors have been limited to 4x in order to achieve compatibility between 26 mm X 33 mm field sizes and 6 inch reticles, and the assumption of large die size. The reduction factor of 4x can be reconsidered if prior predictions of large die size are not realized of capability for making 230 mm reticles becomes available. The economics of 230 mm reticles changes favorably when the reduction factor is increased. Large reduction factors have relatively neutral effects on lens cost, but will make fast scanning more difficult. A proposal for a possible new optimum reduction is given from the analysis of these critical factors.

Business dynamics of lithography at very low k1 factors

Lithography is the largest capital investment and the largest operating cost component of leading edge semiconductor fabs. In addition, it is the dominant factor in determining the performance of a semiconductor device and is important in determining the yield and thus the economics of a semiconductor circuit. To increase competitiveness and broaden adoption of circuits and the end products in which they are used, there has been and continues to be a dramatic acceleration in the industry roadmap. A critical factor in the acceleration is driving the lithographic images to smaller feature size. There has always been economic tension between the pace of change and the resultant circuit cost. The genius of the semiconductor industry has been in its ability to balance its technology with economic factors and deliver outstanding value to those using the circuits to add value to their end products. The critical question today is whether optical lithography can be successfully and economically extended to maintain and improve the economic benefits of higher complexity circuits. In this paper we will discuss some of these significant tradeoffs required to maintain optically based lithographic progress on the roadmap at acceptable cost.