Muhammad Masuduzzaman

Exploring the Capability of Multifrequency Charge Pumping in Resolving Location and Energy Levels of Traps Within Dielectric

Multifrequency charge-pumping (MFCP) experiments have been used by many groups to profile the locations and the energy levels of bulk traps within high-kappa gate dielectric stack of MOS transistors. Since the measurements involve easy generalization of the classical CP technique, the interpretation of the data has sometimes been based on uncritical generalization of classical CP theory or a simplified numerical model that does not capture the complexity and nuances of the dynamics of occupation of dielectric traps. In this paper, we develop a rigorous numerical model of MFCP technique and encapsulate/interpret the results using an intuitively simple analytical formula. Consistent with some earlier reports, we observe that MFCP experiment scans a limited region of traps within the dielectric stack. Although the degree of trap response in MFCP is a (nonintuitive) function of parameters like rise/fall time, frequency, temperature, and pulse levels, we show that only a certain combination of parameters is sufficiently orthogonal to allow unambiguous back-extraction of the trap profile.

Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics

We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.

Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., ION, IOFF, Vth, SS, RC) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔVth, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.

Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target

Effective nanometer airgap of NEMS devices using negative capacitance of ferroelectric materials.

I_{\mathrm{{\scriptscriptstyle ON}}}

Origin and implications of hot carrier degradation of Gate-all-around nanowire III–V MOSFETs

, along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs.

Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs

Nanoelectromechnical system (NEMS) is seen as one of the most promising candidates for next generation extreme low power electronics that can operate as a versatile switch/memory/sensor/display element. One of the main challenges toward this goal lies in the fabrication difficulties of ultrascaled NEMS required for high density integrated circuits. It is generally understood that fabricating and operating a NEMS with an airgap below a few nanometer will be extremely challenging due to surface roughness, nonideal forces, tunneling, etc. Here, we show that by cascading a NEMS with a ferroelectric capacitor, operating in the negative capacitance regime, the effective airgap can be reduced by almost an order of magnitude, without the need to reduce the airgap physically. This would not only reduce the pull-in voltage to sub-1 V regime, but also would offer a set of characteristics which are difficult/impossible to achieve otherwise. For example, one can reduce/increase the classical travel range, flip the traditional stable-unstable regime of the electrode, get a negative pull-out voltage, and thus, center the hysteresis around zero volt. Moreover, one can also operate the combination as an effective ferroelectric memory with much reduced switching voltages. These characteristics promise dramatic saving in power for NEMS-based switching, memory, and other related applications.

Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs

Although ultra-scaled III-V Gate-all-around (GAA) nanowire (NW) MOSFETs have been studied for their immunity to short channel effects, the degradation mechanisms, such as, hot carrier injection (HCI) in the NW MOSFETs are yet to be studied systematically. In this paper, we examine how HCI affects the NW device performance (ΔVth, ΔSS in both stress and recovery) at different bias conditions, and demonstrate that, unlike positive bias temperature instability (PBTI) in NMOS transistors, the HCI degradation is dominated by charge trapping. We analyze the implications of spatial charge trapping on device performance through experiments and simulation. We find that the distinctive features of HCI degradation of GAA NWs structure can be consistently interpreted by a Sentaurus™-based TCAD simulation.

A multi-probe correlated bulk defect characterization scheme for ultra-thin high-к dielectric

Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.

Physics and mechanisms of dielectric trap profiling by Multi-frequency Charge Pumping (MFCP) method

Furthering Si CMOS scaling requires development of high-mobility channel materials and advanced device structures to improve the electrostatic control. We demonstrate the fabrication of gate-all-around (GAA) indium gallium arsenide (InGaAs) MOSFETs with highly scaled atomic-layer-deposited gate dielectrics. InGaAs, with its high electron mobility, allows higher drive currents and other on-state performance compared to silicon. The GAA structure provides superior electrostatic control of the MOSFET channel with outstanding off-state performance. A subthreshold slope of 72 mV/dec, electron mobility of 764 cm2/V·s, and an on-current of 1.59 mA/μm are demonstrated, for example. Variability studies on on-state and off-state performances caused by the number of nanowire channels are also presented.