William F. Landers

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

Vertical channel devices enabled by through silicon via (TSV) technologies

Novel device structures with vertical channels gated by TSVs are demonstrated. The unique device structure is realized in a standard TSV process flow, without new material systems or processes. They can be used for both characterizing the TSV process as well as enable new functions. They can be easily integrated into product designs thus enabling field monitoring.

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.