Munir D. Naeem

Grain growth in copper films exposed to magnetically enhanced plasmas

The effects of low‐energy plasma bombardment have been quantified for the first time. The plasma effects on thin copper films (∼50 nm) have been studied by exposing these films to magnetically enhanced Ar plasmas. The Cu films deposited by different techniques were exposed to plasmas by systematically varying the exposure time and the rf power. The microstructural changes (grain size) in the films were studied using transmission electron microscopy. Grain growth is observed in thin Cu films when the films are exposed to low‐energy (63–114 eV) Ar plasmas. rf power is shown to have a strong influence on the microstructure of Cu films. The microstructural changes in sputtered and evaporated films are quite significant whereas the plasma bombardment has less effect on chemical vapor deposited films. These changes occur very rapidly and cannot be attributed solely to the thermal effects especially at low rf powers (300–500 W). The effect of temperature, however, becomes significant at 700 W. The initial micros...

Evaluation of barriers for B and P diffusion into As-doped polysilicon

Abstract Diffusion barriers are used mainly to prevent ionic contamination and diffusion of interconnect metals into the Si substrate in complementary metal oxide semiconductor devices (CMOS). However, diffusion barriers are equally important in order to prevent B and P diffusion from boro-phospho-silicate glass (BPSG) into highly conductive films like As-doped polysilicon. BPSG is commonly used as a contact level dielectric material because of its superior planarization properties in advanced dynamic random access memory devices (DRAM). Secondary ion mass spectrometry (SIMS) data indicate that B and P from BPSG can diffuse easily into polysilicon during routine annealing without any diffusion barrier. The diffusion of these species affects the sheet resistance of polysilicon. The effectiveness of plasma-enhanced chemical vapor deposited tetraethyl ortho silicate (TEOS) and low-pressure chemical vapor deposited Si3N4 films with varying thickness have been evaluated as barriers to B and P diffusion. The B and P diffusion profiles in polysilicon after annealing have been obtained using SIMS analysis. The experimental data are compared with simulated diffusion profiles. We found a 50 nm thick layer of TEOS to be an effective barrier to B and P diffusion into As-doped poly silicon based on experimental data. The SIMS profiles show an order of magnitude higher concentration of As, B and P at the TEOS and poly-Si interfaces which is attributed to the segregation of dopants at grain boundaries. The SIMS profiles indicate faster diffusion of P towards the interface from the bulk of BPSG in comparison with the results obtained by simulation. Revised diffusion coefficients for B and P in BPSG and poly-Si are determined using the experimental data. The calculated diffusion coefficients for B and P in BPSG are at least 3—4 orders of magnitude higher than the values of these coefficients in SiO2.

Abnormal grain growth in copper films during magnetically enhanced plasma processing

The kinetics of grain growth in thin copper films during magnetically enhanced (ME) plasma processing is monitored. Transmission electron microscopy (TEM) results suggest microstructural evolution characteristic of abnormal grain growth in these films. The kinetics of abnormal grain growth appears to depend on gas pressure in the reactor.

Challenge of 1-Gb DRAM development when using optical lithography

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.