Natsuki Kushiyama

A process-variation-tolerant dual-power-supply SRAM with 0.179µm 2 Cell in 40nm CMOS using level-programmable wordline driver

A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.

A 500-megabyte/s data-rate 4.5 M DRAM

A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte*2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate. >

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

This DRAM features (1) interleaved operation of 16 dependent banks with 1.6 GB/s data rate, (2) flexible mapping redundancy which suits multi-bank memory, and (3) additional-refresh that realizes a low data retention power DRAM.

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<<ETX>>

An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differential I/O buses, laid out in fourth metal over the memory cell arrays, use a 0.3 V differential swing. The SRAM is fabricated in a 0.35 /spl mu/m four-layer metal CMOS process employing a 6-T SRAM cell measuring 5.2 /spl mu/m/spl times/6.6 /spl mu/m. The die measures 13.22 mm/spl times/4.80 mm. The SRAM operates at 295 MHz with a 3.3 V supply, achieving a bandwidth of 9.44 Gbyte/s.

A high random-access-data-rate 4 Mb DRAM with pipeline operation

A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 mu m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs. >

A 295 MHz CMOS 1 M (/spl times/256) embedded SRAM using bi-directional read/write shared sense amps and self-timed pulsed word-line drivers

This SRAM explores the feasibility of the mid-capacity, wideword, very high-speed embedded memories for the over-200 MHz generation of MPUs. The SRAM is fabricated in a 0.35 /spl mu/m CMOS quadruple-metal process. It has 1 Mb capacity and 256 b of full-differential 0.3 V-swing I/O. A bidirectional read/write shared sense amp (BSA) and self-timed pulsed word-line (SPW) are used to reduce power consumption, save chip area, and improve performance.