Nhat Nguyen

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

A 7.5Gb/s receiver has a 3-level DFE architecture to satisfy feedback timing requirements for 10 post-cursor taps. The receiver includes a second-order CDR with partial-response transition data filtering as well as a spectrally gated adaptation engine to prevent equalization updates during poor data patterns. The receiver consumes 136mW in a 90nm CMOS process

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell

An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both directions at a BER of 10-12. The measured energy efficiency for the controller interface cell is 13 mW/Gb/s under nominal operating conditions.

A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40 nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45 ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380 fs rms at the transmitter output and BER <10-14 while consuming 8 mW/Gb/s.

Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

A quad transceiver cell is designed and implemented in 90nm CMOS technology with a 1V nominal supply. To minimize area and power consumption, the cell uses a single dual-loop PLL. Gate-current leakage compensator is used to mitigate gate-current leakage in the PLL loop-filter capacitor. The quad cell consumes 73mW/link at 3.125Gbps with 500mV output swing driving double-terminated links and achieves a peak-to-peak transmit jitter of 42ps at 4Gbps data rate.

Performance Analysis of Edge-based DFE

This paper presents an analysis of edge-based decision-feedback equalization (DFE) and compares its performance to conventional data-based DFE in high-speed serial links. We use the link performance analysis framework in (Stojanovic, 2006) to evaluate these two equalization schemes. Simulation results across 13 backplane channels of various length and configuration show that data-based DFE (D-DFE) always performs better than edge-based DFE (E-DFE)

Power-efficient I/O design considerations for high-bandwidth applications

Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system, the subsequent application of that work to a burst-mode asymmetric interface, and recent research on low-overhead bursting are discussed. Dynamic voltage frequency scaling and efficiency increases enabled by system level interconnect improvements are also considered as important techniques.

An Adaptive Body-Biased Clock Generation System in 28nm CMOS

An adaptive forward body biasing technique is implemented in a clock generation and distribution test chip for memory interface applications to enable wide-range and high-fidelity operation. The proposed clock generation system employs a self-body-biased ring voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to adaptively adjust device body voltages over process and temperature variations. Moreover, a differential body-biasing technique incorporated in a duty cycle corrector (DCC) achieves effective correction range with minimal power overhead. The adaptive self-body-biasing technique extends PLL frequency locking range by more than 20 percent while reducing power supply induced jitter (PSIJ) by maximum 25 percent for increased yield and reliable operation.

Design challenges for high performance and power efficient graphics and mobile memory interfaces

Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in todays systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.