Marko Aleksic

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40 nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45 ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380 fs rms at the transmitter output and BER <10-14 while consuming 8 mW/Gb/s.

A 40-Gb/s serial link transceiver in 28-nm CMOS technology

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm2 per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS

This paper presents a 7-bit 3.2-GHz injection-locked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved by strong injection, as opposed to a relatively weak injection during normal operation, and 2) phase characteristic calibration that allows continuous, infinite-throw phase rotation needed for link timing calibration. The circuit is implemented in a 1-V low-leakage 28-nm CMOS process. Power consumption and area are 1.3 mW and 0.03 mm2.

Extraction of jitter parameters from BER measurements

This paper presents a method for jitter parameter extraction from bit error rate measurements, that can be used as an alternative to the dual-Dirac method. The method offers more accurate estimates of random and deterministic jitter, at the expense of a slight increase in complexity. The model underlying the method can be used for extrapolation of bit error rate to the values that are impractical to measure.

Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure

This paper experimentally investigates substrate noise and its impact on the jitter performance of a low-power memory controller PHY interface using an on-chip substrate noise measurement structure. A previously proven on-chip supply noise measurement method is extended with minimum modification in the sensing front end to characterize the substrate noise. The implemented structure achieves the voltage resolution finer than 150µV/LSB and the measurement bandwidth up to 10GHz. The substrate noise impact on the jitter performance of the low-power PHY interface running at 3.2Gbps is characterized in terms of Substrate Noise Induced Jitter (SNIJ) sensitivity.