Niamh Waldron

Selective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices.

Integration of III-V on Si for High-Mobility CMOS

In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates are generated using a Si template which is prepared by standard STI processing. The Si in the STI trenches is etched and a Ge seed layer grown.

Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment

K.U. Leuven, 3000 Leuven, Belgium We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 Ω.cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to ≤ 300 ˚C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment.

III-V Devices and Technology for CMOS

Abstract In this chapter, advances in the use of III-V materials for both n- and p-MOSFET devices will be reviewed including progress in gate stack technology and its associated reliability. For the full potential of III-V to be realized in advanced CMOS technology nodes, it must be integrated on 300xa0mm wafers in order to leverage the benefits of the high-volume manufacturing techniques and toolsets used in advanced Si-CMOS manufacturing. Therefore, a strong emphasis in this chapter is placed on how III-V devices may be integrated onto a Si platform in order to be deployed in a manufacturable VLSI-compatible flow.

Beyond-Si materials and devices for more Moore and more than Moore applications

In this work, we will review the current progress in high mobility devices and new device architectures. With main focus on (Si)Ge for pMOS and In(Ga)As for nMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed. Next to that, the advantages of tunnel FETs, vertical logic and in general heterogeneous integration will be highlighted.

Advanced channel materials for the semiconductor industry

In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for pMOS and In(Ga)As for nMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed.