G. Eneman

Exploring the limits of stress-enhanced hole mobility

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

This paper shows, for the first time, the successful introduction of recessed, strained Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (/spl mu/RS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

The Impact of Layout on Stress-Enhanced Transistor Performance

This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.

Influence of dislocations in strained Si∕relaxed SiGe layers on n+∕p-junctions in a metal-oxide-semiconductor field-effect transistor technology

We present an investigation of junction leakage in highly doped n+∕p-junctions, fabricated in strained silicon/relaxed SiGe substrates. The leakage is shown to scale linearly with the threading dislocation density of the virtual substrate, which allows to estimate minority carrier generation lifetimes in good agreement with literature values. Even the highest-defective substrates in this work give a junction leakage density below 100mA∕cm2, and are not expected to significantly increase the power consumption of metal-oxide-semiconductor field-effect transistor (MOSFET) technologies. Threading dislocations will increase the junction leakage by ∼1nA in a small number of transistors in MOSFET circuits, but are not expected to have a negative impact on yield.

Impact of Epi-Si growth temperature on Ge-pFET performance

In this study, we report a direct comparison between two Epitaxial silicon processes: 500°C using SiH<inf>4</inf> and 350°C using Si<inf>3</inf>H<inf>8</inf>. Following four different metrics, we demonstrate that the reduction of Silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO<inf>2</inf>interface. However, the Epi Si growth at 350°C with Si<inf>3</inf>H<inf>8</inf> remains beneficial compared to a growth performed at 500°C-SiH<inf>4</inf> especially when thin EOT Ge pFETs are targeted.

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

This paper demonstrates for the first time the integration of an HfO2/TiN/poly gate stack and a recessed SiGe S/D module. It also shows that by combining the SiGe stressor with a compressive nitride contact etch stop layer, it is possible to reach improvements in IDSAT of up to 65%, showing that the various strain mechanisms are additive on advanced gate stacks. This way an IDSAT of 422 muA/mum at 20pA/mum I OFF and VDD = 1.1 V can be obtained when a 25% SiGe S/D module is combined with a 1.5 GPa compressive sCESL layer

Scalability of strained nitride capping layers for future CMOS generations

This paper investigates the layout dependence of strain induced in transistor channels, for technologies that use strained nitride capping layers (or contact etch stop layers - CESL). It is shown that the sensitivity in dense structures will be reduced for thinner nitride capping layers and scaled spacers. In isolated structures, the effects of STI- and CESL-induced stress are additive. Guidelines for CESL-scaling in future technologies are proposed.