Nicolas Dupuis

Silicon Photonic Switch Fabrics in Computer Communications Systems

We discuss silicon photonic switch fabric designs that target data-intensive computing networks, reviewing recent results, and projecting future performance goals. We analyze the achievements of demonstrated hardware in terms of switching time, footprint, crosstalk, and power consumption, concluding that the most crucial metric to improve upon is net loss. We propose integrating semiconductor optical amplifiers into the switch fabric using either flip-chip or wafer-bonding technology, and investigate its potential merits alongside several challenges in implementation. Furthermore, we explore the dominant causes of crosstalk, and discuss manners for reducing it. We perform switch simulations that project a 7-dB reduction in crosstalk, when using a push-pull, rather than a single-ended phase shifter drive scheme. We also evaluate crosstalk effects on transmission performance using a full-link model that incorporates multiple crosstalk-accumulating photonic switch hops. The study demonstrates the degree to which crosstalk may degrade signal integrity after just a few occurrences. Finally, a comparison of four topologies highlights tradeoffs in physical-layer design and scheduling complexity, illustrating the scales that may be accomplished with the simplest topologies, and the device improvements required to achieve the more robust architectures.

A Throughput-Optimized Optical Network for Data-Intensive Computing

Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with todays leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.

Design and Fabrication of Low-Insertion-Loss and Low-Crosstalk Broadband

We present the design, fabrication, and measurement results of low-insertion-loss and low-crosstalk broadband 2 × 2 Mach-Zehnder switches for nanosecond-scale optical data routing applications. We propose a simulation framework to calculate the spectral characteristics of switches and use it to design two switches: one based on directional couplers, the other using two-section directional couplers for broader bandwidth. We show that driving the switch in a push-pull manner enables to reduce insertion loss and optical crosstalk at the expense of the optical bandwidth. We achieve a good correlation between simulations and devices fabricated in IBMs 90-nm photonics-enabled CMOS process. We demonstrate a push-pull drive switch with insertion loss of ~1 dB and an optical crosstalk smaller than -23 dB over a 45-nm optical bandwidth in the O-band. We further achieve a transition time of ~4 ns with an average phase shifter consumption of 1 mW and a heater efficiency of ~25 mW/π.

2\times 2

We present simulation and experimental results on a silicon photonic strictly nonblocking 4 × 4 electrooptic Mach- Zehnder-based switch fabric. We propose a simulation framework based on the transfer matrix approach that enables calculating the transmission spectra of any type of multistage interconnect switch network. The model is used to analyze the spectral characteristics of the switch fabric. We also show experimental results on a fabric designed and fabricated in IBMs 90-nm photonics-enabled CMOS process. The fabric monolithically integrates the CMOS logic, the switch drivers, and all the photonics. We fully characterized all the transmittances of the switch and demonstrate onchip insertion loss between 1.5 and 3 dB and a crosstalk less than -25 dB for all the signal paths.

Mach–Zehnder Silicon Photonic Switches

We present complete characterizations of multimode GaAs photodetectors for high-speed VCSEL-based optical links and compare SiGe receiver IC performances in a 62Gbps back-to-back link for different photodiode designs.

Modeling and Characterization of a Nonblocking

We present a silicon photonics optical link utilizing heterogeneously integrated photonic devices driven by low-power advanced 32-nm CMOS integrated circuits. The photonic components include a quantum-confined Stark effect electroabsorption modulator and an edge-coupled waveguide photodetector, both made of III-V material wafer bonded on silicon-on-insulator wafers. The photonic devices are wire bonded to the CMOS chips and mounted on a custom PCB card for testing. We demonstrate an error-free operation at data rates up to 30 Gb/s and transmission over 10 km at 25 Gb/s with no measured sensitivity penalty and a timing margin penalty of 0.2 UI.

4\times 4

Grating couplers are proposed for polarization-independent coupling of light between a single-mode fiber and a 220-nm-thick channel waveguide on silicon-on-insulator. The grating couplers have nonuniform grating periods that are composed of the intersection or union of a set of two near-optimal TE- and TM-grating periods. The proposed grating couplers have a coupling efficiency greater than 20% and polarization dependent loss (PDL) lower than 0.5 dB within 3-dB bandwidth in design. For the evaluation of the design concept, a fabricated intersection grating coupler has the PDL of less than 0.8 dB within the wavelength range of 1540 to 1560 nm, and the coupling efficiency is ∼18%.

Mach–Zehnder Silicon Photonic Switch Fabric

We present the design and characterization of a novel electro-optic silicon photonic 2×2 nested Mach-Zehnder switch monolithically integrated with a CMOS driver and interface logic. The photonic device uses a variable optical attenuator in order to balance the power inside the Mach-Zehnder interferometer leading to ultralow crosstalk performance. We measured a crosstalk as low as -34.5  dB, while achieving ∼2  dB insertion loss and 4 ns transient response.

Exploring the limits of high-speed receivers for multimode VCSEL-based optical links

We describe Mach–Zehnder-based silicon photonic switch fabrics monolithically integrated with a digital CMOS logic and driver circuitry. We review 2 × 2 Mach–Zehnder switches, 2 × 2 nested Mach–Zehnder switches, and strictly nonblocking 4 × 4 switch fabrics with nanosecond-scale, low-power, low-crosstalk, and low-insertion-loss performances. We also demonstrate fast dynamic reconfigurability on an 8 × 8 butterfly switch fabric. Technical challenges and future research directions of silicon photonic scaled switching systems are also discussed.

30-Gb/s Optical Link Combining Heterogeneously Integrated III–V/Si Photonics With 32-nm CMOS Circuits

We propose a flexible optical transmitter for the short-reach optical interconnects that includes a silicon photonic segmented Mach-Zehnder modulator driven by a distributed six-channel 32-nm silicon on insulator (SOI) complementary metaloxide semiconductor driver integrated circuit. Optical equalization is demonstrated to extend the bandwidth limitation of the transmitter with non-return to zero signaling at 25Gb/ s. We also generate four-level pulse amplitude modulation (PAM-4) signaling using the same transmitter architecture. Transmission of 46 Gb/s PAM-4 signal with bit error rate (BER) well below hard-decision forward error correction limit is experimentally demonstrated. Low driver power consumption of 130 mW at 46Gb/ s PAM-4, corresponding to 2.8 pJ/bit power efficiency, is also achieved.