L. De Michielis

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

In this letter, we report that the source and channel Fermi-Dirac distributions in interband-tunneling-controlled transistors play a fundamental role on the modulation of the injected current. We explain the superlinear onset of the output characteristics based on the occupancy function modulation. Thus, we point out that, along with the tunneling barrier transparency, the availability of carriers and empty states, at the beginning and at the end of the tunneling path, respectively, should be always taken into account for a proper modeling of tunnel FETs.

Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation

In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SS_AVG ~ 13 mV/dec over six decades of current), I_ON/I_OFF ratio of ~ 10⁹, and drive current of I_ON ~ 10 μA/μm at V_DD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with I_ON and I_OFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when V_DD = 0.25 V.

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm2 /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform.

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

Tunneling and Occupancy Probabilities: How Do They Affect Tunnel-FET Behavior?

In this letter, the occupancy and tunneling probabilities of interband tunneling devices are studied, pointing out the fundamental function of the source Fermi-Dirac distribution. Particularly, the reason for the degraded subthreshold swing, which is typical of devices with highly doped source, is explained, and its relation with the high-energy source Fermi tail is carefully analyzed. Simultaneously, the poor driving capability of Tunnel-FET devices is investigated, highlighting the primary role played by the occupancy functions.

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.

An innovative band-to-band tunneling analytical model and implications in compact modeling of tunneling-based devices

In this paper, an analytical band-to-band tunneling model is proposed, validated by means of drift-diffusion simulation and comparison with experimental data, implemented in Verilog-A, and finally proven with SPICE simulator through simulation of circuits featuring tunneling diodes. The p-n junction current calculation starts from a non-local Band-to-Band tunneling theory including the electron-phonon interaction and therefore it is particularly suited for indirect semiconductor materials such as silicon- or germanium-based interband tunneling devices.

The Hysteretic Ferroelectric Tunnel FET

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report Ion/Ioff larger than 105 and Ioff on the order of 100 fA/μm in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO2/Al2O3/ PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature.

Corner Effect and Local Volume Inversion in SiNW FETs

In this paper, a quantitative study of the corner effect and of the local volume inversion on gate-all-around MOSFETs based on numerical simulations has been carried out; different angles and doping levels are compared, in order to understand the impact of the corner regions on the total current. A method for the extraction of the threshold voltage and of the subthreshold slope of the corner region has been proposed, and the resulting values have been analyzed in order to understand their effects on the device characteristics.