Keiichi Numata

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor

We propose a new negative source degeneration resistor (NSDR) transconductor to achieve a wide continuous-tuning range gm-C filter applicable for IEEE802.11a/b/g wireless-LANs and W-CDMA. The NSDR-transconductor using a source degeneration resistor and positive feedback differential amplifier that acts as a negative resistor. This configuration enables the equivalent source degeneration resistance to be drastically increased without degrading linearity, thus resulting in a wide gm tuning. A 6th -order elliptic low-pass filter using this NSDR-transconductor exhibits a cutoff frequency (f/sub c/) tuning range of 1.5-12MHz, which is two times wider than that of conventional filters. Additionally, we introduce a new figure of merit (FoM) evaluating the basic filter performance. This filter shows 0.35 fj (FoM) in the IEEE802.11a mode, which is, to our best knowledge, the best value in the CMOS channel-select filters.

A high-power-handling GSM switch IC with new adaptive-control-voltage-generator circuit scheme

We propose a high-power-handling switch circuit using a new adaptive-control-voltage-generator circuit (AVG). This AVG enables the internal control node voltages to be automatically increased in high-input-power conditions. This switch circuit results in high-power-handling, low-insertion-loss, small chip size and low voltage control. The developed IC demonstrated a handling power of 36.5 dBm and an insertion loss of 0.31 dB with 40% chip size reduction.

A +2.4/0 V controlled high power GaAs SPDT antenna switch IC for GSM application

We have developed a high-power-handling and low-voltage-controlled GaAs single-pole dual-throw (SPDT) antenna switch for GSM application. The switch circuit configuration has a capacitor at the antenna terminal and two resistors between the transmitter (Tx) and receiver (Rx) terminals and the control terminals. This circuit enables the DC voltages of the Tx terminal and the Rx terminal to be separated from each other, resulting in a high-power-handling operation at a lower control voltage than that for the conventional switch. The developed SPDT switch demonstrated a handling power of 37.5 dBm and an insertion loss of 0.37 dB with a control voltage of +2.4/0 V.

0.6 V suppy voltage 0.25 /spl mu/m E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

A new technology for fabricating 0.25 /spl mu/m gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultralow supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 /spl mu/m gate opening through the use of optical lithography and inner SiO/sub 2/ sidewalls. The f/sub max/ and the g/sub max/ for a Y-shaped gate E-HJFET are 108 GHz and 530 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1 mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.<<ETX>>

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

A novel high-speed low-power tri-state driver flip flop (TD-FF) for ultra-low supply voltage GaAs heterojunction FET LSIs

The authors describe a new GaAs static flip flop, called TD-FF (tri-state driver flip flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FFs so far. The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.<<ETX>>

Ultra low power consumption heterojunction FET 8:1 MUX/1:8 DEMUX for 2.4 Gbps optical fiber communication systems

A gallium arsenide 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4 Gbps optical communication systems have been developed. These LSIs employ a tree-type architecture using 2:1 MUXs/1:2 DEMUXs that is suitable for high-speed and low power operation but requires precise control of clock timing. To ensure timing margins, a new timing generator and clock buffer circuit have been developed. These LSIs operate at over 2.4 Gbps with 150-mW of power consumption at a supply voltage of 0.7 V.

A 10 Gb/s optical transmitter module with a built-in modulator driver IC and a receiver module with a built-in preamplifier IC

We have fabricated and tested an optical transmitter module with a built-in modulator driver IC and a receiver module with a built-in preamplifier IC, both designed for use in 10 Gb/s optical communication systems. Newly developed circuits enabled high-speed transmitter modulation characteristics with short rise and fall times of 18 ps and 21 ps, respectively, and a low-power consumption of 1.1 W. High-sensitivity of -26.1 dBm and a wide-bandwidth of 9.2 GHz were obtained from the receiver. Using a transmitter and receiver pair, we obtained back-to-back sensitivity of -24.8 dBm, and power penalties of 0.8 dB over a 60 km single-mode-fiber (SMF) transmission and 1.7 dB over an 80 km SMF transmission. The sensitivity over the 80 km SMF transmission, and these power penalties, are the best yet reported.