Noriaki Matsuno

Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor

We propose a new transconductor to achieve a wide continuous-tuning-range filter applicable to IEEE802.11a/b/g W-LANs, W-CDMA, and Bluetooth, without sacrificing power consumption. The wide tuning range is achieved by employing triode-biased input MOSFETs, whose transconductance is widely tuned with drain bias. The transconductor also employs an adaptive DC-blocking circuit that suppresses any idle current in the high transconductance mode, resulting in minimizing the power consumption of the transconductor. A 4th-order Butterworth low-pass filter, using this new transconductor, exhibits a cutoff frequency tuning range of 0.5-12 MHz with power consumption of 1.1-4.7 mW. The tuning range is 5 times wider than other works with low power consumption.

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor

We propose a new negative source degeneration resistor (NSDR) transconductor to achieve a wide continuous-tuning range gm-C filter applicable for IEEE802.11a/b/g wireless-LANs and W-CDMA. The NSDR-transconductor using a source degeneration resistor and positive feedback differential amplifier that acts as a negative resistor. This configuration enables the equivalent source degeneration resistance to be drastically increased without degrading linearity, thus resulting in a wide gm tuning. A 6th -order elliptic low-pass filter using this NSDR-transconductor exhibits a cutoff frequency (f/sub c/) tuning range of 1.5-12MHz, which is two times wider than that of conventional filters. Additionally, we introduce a new figure of merit (FoM) evaluating the basic filter performance. This filter shows 0.35 fj (FoM) in the IEEE802.11a mode, which is, to our best knowledge, the best value in the CMOS channel-select filters.

PAE enhancement by intermodulation cancellation in an InGaP/GaAs HBT two-stage power amplifier MMIC for W-CDMA

We developed an InGaP/GaAs heterojunction bipolar transistor (HBT) two-stage power amplifier monolithic microwave integrated circuit (MMIC) for 1.95-GHz W-CDMA. In this MMIC, intermodulation distortion (IMD) cancellation between the driver- and final-stage HBTs occurs, so we can reduce an adjacent-leakage-power-ratio (ACPR) and enhance power-added efficiency (PAE) by balancing the bias currents for each stage. The MMIC has a high PAE of 44%, an output power of 26.0 dBm, and a gain of 27.9 dB with ACPR of -35 dBc at a 5-MHz offset frequency under a supply voltage of 3.6 V. This PAE represents state-of-the-art performance of HBT MMICs for W-CDMA.

Effect of gain expansion on power HBTs

This paper describes the effect of gain expansion on power heterojunction bipolar transistors (HBTs). Gain expansion improves the power-added efficiency of power amplifiers in the high-input-power region under the CDMA criteria because the gain expansion compensates for the gain compression in the high-input-power region. RF simulation showed that the gain expansion of HBTs is caused by increased maximum stable gain in the low-collector-current region. Class-B operation was found to enhance gain expansion due to the transconductance drastically increasing with the collector current in the class-B operation region.

Low-Power Widely Tunable Gm-C Filter Employing an Adaptive DC-blocking, Triode-Biased MOSFET Transconductor

We propose a transconductor capable of providing a wide continuous-tuning-range filter applicable to Bluetooth, W-CDMA, LTE, and IEEE 802.11a/b/g W-LANs without sacrificing power consumption or die area. The wide tuning range is achieved without the need for any array configuration, using triode-biased input MOSFETs with transconductance that is widely tunable by means of drain bias adjustment. The transconductor also uses an adaptive DC-blocking circuit that suppresses bias current in a high transconductance mode, which results in minimizing transconductor power consumption.A 4th-order Butterworth low-pass filter using this transconductor, fabricated in a 0.18-μm CMOS process, exhibits a cut-off frequency tuning range of 0.3-12 MHz with a current consumption of 0.6-2.6 mA. The die area is small: 0.125 mm2.

A New DC-Offset and I/Q-Mismatch Compensation Technique for a CMOS Direct-Conversion WLAN Transmitter

This paper presents a novel DC-offset and I/Q-mismatch compensation technique with short convergence time, high accuracy, and low-circuit-complexity. In this technique, all kinds of transmitter nonidealities, i.e. an offset and a mismatch, can be detected using adequate pair of DC test signals. The test signals are designed so that the envelope of the modulator RF outputs for each test signal fluctuates when the offset or mismatch exists. The fluctuations are converted to a baseband signal using an envelope detector which is designed as a signal dynamic range compressor to avoid saturation in following stages. The polarity of this fluctuation is detected by a comparator instead of a multi-bit analog to digital converter, and a binary-search-type algorithm optimizes parameters for the offset and mismatch compensation using the 1-bit comparator output. This technique was demonstrated in a 0.18-mum CMOS 5-GHz-band WLAN transmitter. The DC offset was suppressed to -43 dBc and the image tone was suppressed to -49 dBc.

0.2-/spl mu/m fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-/spl mu/m, high-aspect-ratio, Y-shaped-gate heterojunction-FETs (HJFETs) with about half the external gate-fringing capacitance (C/sub f//sup rext/) of conventional Y-shaped gate HJFETs. The 0.2-/spl mu/m Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO/sub 2/ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-/spl mu/m gate n-Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.2/Ga/sub 0.8/As HJFET shows very small current saturation voltage of 0.25 V, marked gm/sub max/ of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f/sub T/=71 GHz and f/sub max/=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C/sub f//sup rext/. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog ICs/LSIs.

A 500-mW high-efficiency Si MOS MMIC amplifier for 900-MHz-band use

A 500-mW monolithic-microwave integrated-circuit (MMIC) amplifier using a 0.6-/spl mu/m Si MOSFET for 900-MHz-band use has been developed. The input matching network, which consists of a spiral inductor and an MOS capacitor, was integrated onto the chip using a low-cost mass-production large-scale-integration process. A new spiral-inductor model, taking into account the dielectric loss and skin effect of the Si substrate, was introduced. We analyzed the stability and gain dependence on the gate structure of the MOSFET and optimized the gate finger length and the loss of the matching network to achieve high gain and stability. The fabricated MMIC amplifier achieved a linear gain of 15.2 dB and an output power of 27.1 dBm with a PAE of 60% under a supply voltage of 4.8 V.