Nobuhiko Mutoh

Technologies to improve photo-sensitivity and reduce VOD shutter voltage for CCD image sensors

New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p/sup +/-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers.

New low noise output amplifier for high definition CCD image sensor

A novel low-noise CCD (charge coupled device) output amplifier, the RJG detector, has been developed. The RJG detector incorporates a JFET having an electrically floating ring-junction gate (RJG). The operating principle is that signal charges, transferred from CCD into the RJG, directly modulate the drain current in the detection JFET. Test devices were fabricated and evaluated with 37-MHz clock frequency. By introducing JFET and achieving complete charge transfer in reset operation, 1/f noise has been reduced and reset noise has been completely eliminated. As a result, input referred noise equivalent electrons within the 18.5 MHz baseband were reduced to 17 (electrons). The RJG detector is confirmed to be suitable for a high-definition CCD image sensor, which requires high-speed operation.<<ETX>>

A 2/3-inch 2 M-pixel IT-CCD image sensor with individual p-wells for separate V-CCD and H-CCD formation

This 2/3-inch optical-lens-format, 2 M-pixel interline-transfer (IT) CCD image sensor achieves large charge handling capability in the vertical CCD (V-CCD), and at the same time ensures sufficient transfer efficiency in the horizontal CCD (H-CCD). A V-CCD/H-CCD connection eliminates the potential barrier caused by separate V-CCD/H-CCD formation. Image sensor performance includes a 40 k-electron charge-handling capability in the V-CCD, leading to a 71 dB dynamic range, and sufficient transfer efficiency in the H-CCD, with no deterioration in V-CCD to H-CCD transfer efficiency. The power consumption is 0.49 W, just 22% of that previously achieved in a 1-inch 2 M pixel frame interline transfer (FIT) CCD. This is possible because the p-well reduces the driving pulse amplitude in the V-CCD and the IT scheme decreases electrode capacitance and driving frequency.<<ETX>>

A 1920(H)*1035(V) pixel high-definition CCD image sensor

A 1920(H) × 1035(V) pixel high definition CCD image sensor has been developed. In order to follow up 74.25 MHz high sampling frequency, as well as to avoid the necessity for ultra fine patterning work for horizontal CCD register electrode formation, the device adopts a dual channel configuration for the horizontal CCD register. To accomplish both vertical signal charge transfer in the V-CCD register and signal charge distribution from the V-CCD registers into the dual channel horizontal CCD registers simultaneously within a 3.77 ¿s short horizontal blanking period, the 1H memory electrode between the V-CCD and H-CCD is introduced. The device operates successfully and a 1000 TV line limiting resolution has been obtained.

A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV). >

Thermionic-emission-based barrier height analysis for precise estimation of charge handling capacity in CCD registers

In designing charge-coupled device (CCD) image sensors, it is essential to be able to estimate charge handling capacity. Because electrons have thermal energy, storing electrons in a well in a CCD register requires a sufficient potential barrier height to keep them from overflowing. As the quantity of electrons in a well depends on the barrier height, knowledge of this height is indispensable for precise estimation of the charge handling capacity. The authors have derived an expression describing the barrier height on the basis of thermionic emission, assuming current coefficient I/sub 0/ and well capacitance C. We derived the current coefficient I/sub 0/ and well capacitance C with computer simulations and from the results estimate the magnitude of the barrier height for a typical Vertical-CCD (V-CCD) structure. We have also examined barrier height dependence on structural parameters. Finally, we determined the barrier heights experimentally, and our results support the values obtained in the simulation.

New empirical relation for MOSFET 1ƒ noise unified over linear and saturation regions

Abstract This paper proposes an empirical relation, which represents 1 ƒ noise bias condition dependence for a silicon N -channel MOSFET. No matter whether the MOSFET is operated in linear or saturation region, bias condition dependence is found to be well described by a power function of voltage gain. By introducing a devices intrinsic 1 ƒ noise emf v nc (ƒ) , which is independent from bias condition, and empirical parameter β, input-referred 1 ƒ noise voltage v ni (ƒ) is clarified to be a function of v nc (ƒ) , β, and voltage gain g m g DS , i.e. v nc (ƒ)( g m g DS ) β−1 . This relation implies that 1 ƒ noise voltage depends implicitly on bias condition through voltage gain, because transconductance g m and drain-source differential conductance g DS depend on bias condition. If β − 1 value is negligible, v ni (ƒ) = v nc (ƒ) is almost independent from bias condition, whereas, if β − 1 value is not negligible, bias condition dependence for v ni (ƒ) appears to be observed. The β deviation from unity, which characterizes bias condition dependence, measures the difference between signal amplification and 1 ƒ noise amplification.

Optical limitations to cell size reduction in IT-CCD image sensors

We have determined the practical limits of cell size reduction in interline-transfer CCD image sensors, limits resulting from diffraction occurring at the aperture above the photodiode. We have found that image cell size cannot be reduced to a level for which aperture width would fall below about 0.2 /spl mu/m. We have also found, however, that image cells with greater than 0.2 /spl mu/m aperture size are sensitive over the entire wavelength range of visible light, and that sensitivity can be increased by thinning the photoshield film.

Photo response analysis in CCD image sensors with a VOD structure

Photo response in CCD image sensors with Vertical-Overflow-Drain (VOD) was analyzed in an attempt to discover a way to lessen the photo response rise that accompanies increasing incident light intensity in the saturation region. A photo response analysis based on transistor I-V characteristics revealed that the extent of rise in the saturation region is uniquely determined by the non-ideality factor and temperature. Calculation of the non-ideality factor and its dependence on P-well impurity concentration and layer thickness further revealed that fabrication of P-wells with lower impurity concentrations and thicker layers would be effective in suppressing photo response rise. >

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.