Yukiya Kawakami

Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation

We investigated the SRAM soft error rate (SER) by using neutron irradiation testing and computational modeling. Experimentally observed multibit-error patterns can be clarified by our detailed SRAM upset model derived from the 3D device-circuit mixed-mode simulation. This work describes several essential key issues for predicting SER accounting for practical SRAM circuit-layout design issues.

A 2/3-inch 2 M-pixel IT-CCD image sensor with individual p-wells for separate V-CCD and H-CCD formation

This 2/3-inch optical-lens-format, 2 M-pixel interline-transfer (IT) CCD image sensor achieves large charge handling capability in the vertical CCD (V-CCD), and at the same time ensures sufficient transfer efficiency in the horizontal CCD (H-CCD). A V-CCD/H-CCD connection eliminates the potential barrier caused by separate V-CCD/H-CCD formation. Image sensor performance includes a 40 k-electron charge-handling capability in the V-CCD, leading to a 71 dB dynamic range, and sufficient transfer efficiency in the H-CCD, with no deterioration in V-CCD to H-CCD transfer efficiency. The power consumption is 0.49 W, just 22% of that previously achieved in a 1-inch 2 M pixel frame interline transfer (FIT) CCD. This is possible because the p-well reduces the driving pulse amplitude in the V-CCD and the IT scheme decreases electrode capacitance and driving frequency.<<ETX>>

A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV). >

A 32b floating point CMOS digital signal processor

A 1.5μm CMOS digital signal processor with 150ns instruction cycle time will be reported. The chip contains a 32b floating point parallel multiplier and a 55b floating point ALU. The IC contains 370K transistors.

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.

A 1-inch 2-M pixel HDTV CCD image sensor with tungsten photo-shield and H-CCD shunt wiring

A 1-inch 2-million pixel FIT-CCD image sensor for HDTV has been developed, which features a tungsten photo-shield and horizontal CCD (H-CCD) shunt wiring. Tungsten photo-shield, which has low reflectance and good step coverage characteristics, reduces smear level to -110 dB, combined with a frame-interline-transfer (FIT) scheme. The tungsten photo-shield also acts as a shunt busline, supplying transfer pulses to vertical CCD (V-CCD) electrodes, so that a 1.2/spl times/10/spl circ/5 electron charge handling capability is obtained at a frame transfer frequency of 1 MHz. Newly developed H-CCD shunt wiring suppresses vertical line pair FPN, even with smaller transfer pulse amplitudes. H-CCD shunt wiring also helps reduce power consumption in the H-CCD by 2/3 as compared to that achieved with conventional wiring. >

A new comprehensive SRAM soft-effor simulation based on 3D device simulation incorporating neutron nuclear reactions

A new SRAM soft-error simulation tool has been developed and its accuracy was evaluated through both acceleration tests for /spl alpha/-particles and energetic neutron beam irradiations. This simulation was able to reproduce the measurement data for the soft-error rate of a 0.15-/spl mu/m SRAM (test-chip) within a factor of two, including the power supply voltage dependency. The simulation system consists of several sub-parts, and features a new data-set for neutron/silicon-atom nuclear reactions and the use of a three-dimensional device simulator for calculating precise charge collection amounts. This accurate simulation can be used for quantitative evaluation of competing effects by means of reduced critical charges and cell-area reduction, and have applications in developing future SRAM technology.

Driving voltage reduction in a two-phase CCD by suppression of potential pockets in inter-electrode gaps

This study reports an optimum design for a two-phase charge-coupled device (CCD) and limitations on its driving voltage reduction. The two-phase CCD to be used as a horizontal-CCD (H-CCD) in a CCD image sensor requires low-voltage and high-speed operation. Reducing the driving voltage, however, may induce potential pockets in the channel under the inter-electrode gaps which results in a fatal decrease in charge-transfer efficiency. In this case it is necessary to optimize the CCD design to be free of pocket generation. For this requirement, we conducted two-dimensional (2-D) device simulations for the two-phase CCD, whose potential barriers are formed by boron ion-implantation. Our simulations indicated that the edge position of the potential barrier region and the dose of boron-ion implantation would be important parameters for controlling the size of potential pockets. At an optimum edge position and a boron dose, the minimum driving voltage appears to be reducible to 1.1 V. Characteristics of potential pockets and methods of their suppression are also discussed.

A 30 frames/s 2/3-in 1.3 M-pixel progressive scan IT-CCD image sensor

A 30 frames/s 2/3-in 1.3 M-pixel progressive scan interline-transfer charge-coupled device (IT-CCD) image sensor has been developed for video and digital still-camera applications. To obtain high frame-rate images, a 49-MHz driving horizontal CCD (H-CCD) was developed. An 8-phase drive for vertical CCDs (V-CCDs) makes it possible to operate in a variety of modes, such as 1050 line progressive scan mode and 1049 line wide dynamic range interlaced scan mode. For digital still camera use, removing residual charges stored in the V-CCDs before exposure is essential, therefore new narrow-channel barrier over-flow drain (NCB-OFD) attached under the H-CCD was developed. The NCB-OFD automatically drains out extra charges and has the advantages of requiring neither an over-flow control gate nor any additional masks.

A 30 frame/s 2/3 inch 1.3M pixel progressive scan IT-CCD image sensor

For multimedia applications, 30Frame/s 2/3 inch 1.3M pixel progressive scan interline-transfer CCD (IT-CCD) image sensor employs an optimized well for the horizontal CCD (H-CCD) and a wide bandwidth amplifier for 49 MHz operation. An 8-phase drive for vertical CCDs (V-CCDs) makes it possible to carry out a variety of operations such as 1050 line progressive mode and 1049 line wide dynamic range interlaced mode. For still camera use, removing residual charges stored in the V-CCDs before exposure is essential. A narrow-channel barrier overflow drain attached under the H-CCD automatically drains extra charge and requires neither overflow control gate nor additional masks.