Nobuhiro Konishi

Influence of post-CMP cleaning on Cu interconnects and TDDB reliability

The etching amount of Cu wires produced by post-chemical-mechanical polishing cleaning was studied. By using polyvinyl alcohol brush cleaning, the cleaning strength concentrates on the center chip of the wafer, which leads to the erosion of Cu interconnects. The etching depths of isolated Cu wires and dense Cu wires were compared. The surface on the isolated Cu wires is etched deeply because of the nonliner diffusion of the solution and the difference between the friction strengths of both wire patterns. These etching depths were improved by optimizing the brush formation, the rotation speed of the roller and the brush, and by using organic-acids. With respect to the dependence of time-dependent dielectric breakdown (TDDB) lifetime on waiting time, there is a difference between the diluted hydrofluoric-acid (DHF) and organic-acid solutions. The TDDB lifetime for the DHF cleaning is similar until after a waiting time of ten days, whereas the TDDB lifetimes for organic-acids are similar until after a waiting time of four days.

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

Influence of CMP Slurries and Post-CMP Cleaning Solutions on Cu Interconnects and TDDB Reliability

We investigated Cu/low-k integration to test the time-dependent dielectric breakdown (TDDB) reliability of Cu interconnects. We described the relationship between TDDB lifetime and defects possibly caused by the Cu chemical-mechanical polishing (CMP) process, such as rough copper surface corrosion, crevice corrosion, and scratches, using Cu/silicon oxycarbide interconnects. Although rough copper surface corrosion has an insignificant effect on the TDDB lifetime, crevice corrosion at the edges of wires does cause TDDB degradation. We also found that a structures TDDB lifetime was affected by the kind of post-CMP cleaning solutions used when barrier metal slurries do not contain benzotriazole (BTA). These results indicate that two types of processes for post-CMP cleaning should be used. It is best to use solutions that do not have strong oxidized copper dissolution ability but can remove particles when a barrier metal slurry with an inhibitor other than BTA is used. Also good are solutions with a strong oxidized copper dissolution ability that have been optimized to prevent Cu corrosion when a barrier metal slurry with BTA is used. To improve TDDB reliability, care must be taken with regard to the combination of the barrier metal slurry and the post-CMP cleaning solution.

Frictional Characterization of Chemical–Mechanical Polishing Pad Surface and Diamond Conditioner Wear

We evaluated a contact metrology instrument used in chemical–mechanical polishing (CMP) systems for high-volume manufacture and examined in situ coefficient of friction (COF) monitoring to identify the tribology of CMP, and subsequently to determine the useful lifespan of consumables. The results showed that the direct measurement of the wear of the pad allowed for an accurate determination of both pad thickness and the ideal time to replace the pad and conditioner disk based on pad wear rate. We also presented a clear correlation between the working grid area of the conditioner disk and the tribological behavior of the pad break-in procedure, leading to the result showing that the variation in tungsten film removal rate decreased as the working grid density of the conditioner disk increased. This study has proven the effectiveness of measuring friction force for better CMP control.

Integration and reliability of Cu-SiOC interconnect for ArF/90-nm node CMOS technology

Cu-SiOC interconnects for ArF/90-nm node technology were investigated. This paper describes the integration and reliability issues. The methods to improve chemical mechanical polishing delamination, SiOC damage and electrical shorts through the bottom interface of Cu interconnects were discussed. Reliability characteristics, such as stress-migration, electro-migration, and time-dependent dielectric breakdown (TDDB) were studied. Cu diffusion with via resistance increase by high-temperature stress, and TDDB degradation due to the ArF process were found. It was confirmed that the suggested integration process was mature and sufficiently reliable for normal operating conditions.

Analysis of Post-Chemical-Mechanical-Polishing Cleaning Mechanisms for Improving Time-Dependent Dielectric Breakdown Reliability

Using Cu/SiOC interconnects, we investigated the relationship between the time-dependent dielectric breakdown (TDDB) reliability and the cleaning process in copper chemical-mechanical polishing (CMP). We found that the formation of a nonuniform copper oxide film during post-CMP cleaning causes TDDB degradation when a barrier metal slurry that does not contain benzotriazole is used. We also found the reformation of a nonuniform copper oxide layer that accompanies the deionized water rinse is due to the dissolution of too much of the copper oxide film during the post-CMP cleaning process. For improved TDDB reliability, the uniform copper oxidization during the post-CMP cleaning process is important in the Cu/low-k damascene integration process.

Novel dissoluble hardmask for damage-less Cu/low-k interconnect fabrication

A Cu/low-k dual-damascene process using a novel dissoluble hardmask material, AlO, is developed to suppress ashing-damage to porous/nonporous low-k SiOC. In this process, ArF-resist patterns are firstly transferred to a very thin, typically 30-nm-thick, AlO hardmask layer. After removing the resist, SiOC is patterned using the hardmask. The hardmask remaining after the etching is spontaneously removed during post-etch wet-cleaning. The line-to-line capacitance of 280-nm-pitch, 4-level interconnects using this process is reduced by 10% from that using a conventional resist-mask process.

Tribological Behavior of Metal CMP and Detection of Process Abnormality

We examined a real-time coefficient of friction (COF) monitoring to evaluate the correlation between the pad surface response during polishing and material removal rate for metal chemical-mechanical polishing (CMP) applications. The results showed that a correlation of the removal rate and COF in tungsten (W) CMP was contrary to that in copper (Cu) CMP. Polishing by-products generated during CMP affects the friction force between the probing tip and the pad surface. The balance between the chemical and mechanical factors indicates the different frictional behavior between W CMP and Cu CMP. Furthermore, we detected the failures in the CMP process, which extracts an out-of-range deviation of the continuously monitored COF in product wafers, and reveal them in tantalum CMP. These results demonstrated the usefulness of an in situ CMP process monitor.

Dual-Damascene Cu/Low-k Interconnect Fabrication Scheme Using Dissoluble Hard Mask Material

A Cu-low-k dual-damascene scheme is developed by employing a dissoluble hard mask material, AlO. High-selectivity etching, over 15, is achieved by using the AlO hard mask. After the etching, the remaining AlO dissolves ina postetch cleaning solution, making additional processing costs minimal. By using this scheme, the line-to-line capacitance reduces by 10% because no ashing is applied after low-k trench etching. Low-temperature deposition of AlO is found to be the key for the dissoluble property. When the deposition temperature is 100°C or less. a wide range of conventional postetch cleaning solutions can be used to remove the remaining AlO hard mask.

Ultra Low-Temperature Growth of High-Integrity Thin Gate Oxide Films by Low-Energy Ion-Assisted Oxidation.

High integrity thin gate oxide films have been grown at a temperature as low as 450° C by direct oxidation of silicon. The bombardment of the silicon surface by low energy ions of argon and oxygen mixed plasma is utilized to activate the oxidation process. Dielectric breakdown field intensity of the oxide film of 12 MV/cm is obtained by the MOS capacitor evaluation. The precise control of the bombarding energy is essential in achieving the high-integrity thin gate oxide films.