Taishi Kubota

A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far.<<ETX>>

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed. >

Constant Current Stress Breakdown in Ultrathin SiO2 Films

Ultrathin dielectric films play an important role in Integrated Circuits (ICs), both as gate dielectrics for MOS technologies, and as tunnel dielectrics for erasable memory (e.g. EEPROM) technologies. Therefore, significant effort has been directed towards understanding degradation and dielectric breakdown in these films [1, 2, 3]. One of the primary causes of degradation is electrical stress that the dielectric is subjected to during device operation, either by design (as in the case of tunnel dielectrics), or as an undesired effect (as in the case of hot-electron stressing of gate dielectrics in MOS transistors). Film thickness and temperature of operation also sensitively affect dielectric breakdown. Understanding the impact of the former becomes important as dielectrics are scaled to lower thicknesses, while the latter is important for ICs in automobiles, and other applications where the operating temperature is high.

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain size must be shrunk proportional to the cell size. A process technology breakthrough will have to be achieved to form smaller size grains because 16 M will be the maximum capacity using current process technology with this new theory. It is also shown how 64 M flash memories can be achieved without such a technology breakthrough.<<ETX>>

Bias-temperature degradation of pMOSFETs: mechanism and suppression

We investigated pMOSFET Bias-Temperature (BT) degradation by using carrier separation analysis. Electrons tunneling from gate electrode to substrate were found to cause impact ionization at the SiO/sub 2//Si interface and result in the creation of trapped charges and interface states. A higher-concentration boron incorporation into the SiO/sub 2/ film was found to suppress BT degradation. This is considered to be a result of tunneling electron current suppression. Degradation due to BT can also be suppressed by reducing the electric field in the oxide between the gate electrode and drain. In other words, BT degradation is lower for the ON-state than the OFF-state. The electric field between the gate electrode and drain can also be reduced by changing the side wall formation process.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new DRAM cell structure, based on a new design concept, and a fabrication technology for DRAMs of 16Mbits and beyond are proposed. The proposed cell, called a transistor on a lateral epitaxial (TOLE) silicon layer cell, can achieve high immunity to alpha-particle-induced soft errors and a low parasitic bit line capacitance. The TOLE cell is produced by a silicon-on-insulator (SOI) fabrication technology newly developed by combining epitaxial lateral overgrowth(1)(ELO) and preferential polishing(2)(PP). Reasonable electrical characteristics for the TOLE transistor and excellent immunity against alpha-particle disturbance for the TOLE memory cell are confirmed.

The effect of the floating gate/tunnel SiO/sub 2/ interface on FLASH memory data retention reliability

The influence of phosphorus at the floating gate (FG)/tunnel oxide interface on the FLASH memory data retention characteristics is investigated. By measuring the electrical characteristics of memory cells and MOS capacitors, it was found that there is a close relationship between the memory cell data retention and stress induced leakage current (SILC). Lowering the phosphorus density in the FG is found to have the effect of suppressing SILC and prolong the data retention. In addition, applying amorphous Si (a-Si) to the FG is also found to improve SILC. The memory cell data retention characteristics is expected to improve when a-Si is applied to the FG. This a-Si FG benefit is investigated by C-V characteristics, SIMS and EDX analysis. In spite of the high impurity activation ratio, the phosphorous concentration at the FG/tunnel oxide interface was confirmed to be lower for the a-Si FG than for the poly-Si FG. Applying a-Si therefore, is confirmed to have the same effect as lowering the phosphorus concentration in the FG but preventing the gate depletion effect. This attractive phenomenon for a-Si may be resulting from the lower phosphorus diffusion along the grain boundary. a-Si therefore is the most promising material for high reliability FLASH memories.

A CMOS/partial-SOI structure for future ULSIs

An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<<ETX>>

FLASH memory data retention reliability and the floating gate/tunnel SiO2 interface characteristics

Abstract The influence of phosphorus at the floating gate (FG)/tunnel oxide interface on the FLASH memory data retention characteristics is investigated. By measuring the electrical characteristics of memory cells and MOS capacitors, a close relationship was found between the memory cell data retention and stress induced leakage current (SILC). Lowering the phosphorus density in the FG suppresses SILC and prolong the data retention. Applying amorphous Si (a-Si) to the FG, in addition is also found to improve SILC. Thus the memory cell data retention characteristics are expected to be improved when a-Si is applied to the FG. This a-Si FG advantage is investigated by C–V characteristics, SIMS and EDX analysis. In spite of the high impurity activation ratio, the phosphorous concentration at the FG/tunnel oxide interface was confirmed to be lower for the a-Si FG than for the poly-Si FG. Applying a-Si therefore, is confirmed to have the same effect as lowering the phosphorus concentration in the FG but preventing the gate depletion effect. This attractive phenomenon for a-Si may result from the lower phosphorus diffusion along the grain boundary. a-Si therefore is the most promising material for high reliability FLASH memories.

A 0.54 /spl mu/m/sup 2/ self-aligned, HSG floating gate cell (SAHF cell) for 256 Mbit flash memories

A 0.54 /spl mu/m/sup 2/ self-aligned memory cell with hemispherical-grained (HSG) poly-Si floating gate (SAHF cell) has been developed for 256 Mbit flash memories. Applying hemispherical-grained (HSG) poly-Si to floating gate extends the upper surface area to double that of the floating gate in comparison with the conventional ones. A high capacitive-coupling ratio of 0.8 and buried n/sup +/ diffusion layers which are self-aligned to the floating gate poly-Si are realized simultaneously with a simple cell structure and fewer process steps.