Norio Endo

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.

An 80 ns 1 Mbit MASK ROM with a new memory cell

A high-speed 1-Mb MASK ROM incorporating a new through-hole programmed memory cell, named THOLE CELL, and a full CMOS static sense amplifier is described. The ROM has been fabricated using a double-polysilicon p-well CMOS technology. As a result of achieving a compact ROM cell that is as small as 5.2-/spl times/6.4 /spl mu/m/SUP 2/, even with relatively conservative 2.0 /spl mu/m design rules, a small die size of 7.08/spl times/7.7 mm/SUP 2/ is realized. The ROM organization is 128K/spl times/8 bit and has a typical access time of 80 ns. A typical active current of 8 mA is achieved, in spite of the fully static system. This ROM offers high speed and low power characteristics, while achieving small die size and short turnaround time.

N-Channel High Speed Nonvolatile Static RAM Utilizing MNOS Capasitors

An improved n-channel nonvolatile static RAM is proposed by introducing a new memory cell which consists of a pair of MNOS capacitors and a 6-transistor MOS flipflop circuit. The RAM can be operated as a high speed static memory under a stable power supply, and as a nonvolatile memory by externally applying erasing/writing signals to a common MNOS gate signal line. Self-generation of inhibiting voltage by bootstrapping effect of MNOS capacitors enables this memory to operate with a single power supply of 5 V. Fully decoded 16-bit experimental devices are fabricated and evaluated. This technology shows the possibility to realize a high packing density memory of 4 K-bit or beyond with the access time of less than 100 ns using 3 µm design rule.

An 80ns 1Mb ROM

This paper will describe a 1Mb programmable ROM incorporating a through-hole programmed mask ROM cell and a CMOS fully static sense amp. The ROM has been fabricated using a double poly-Si P-well CMOS technology, achieving a cell size of 33μm2.

A new mask ROM cell programmed by through-hole using double polysilicon technology

A new through-hole programmed MASK ROM cell which is suitable for 1Mbit high speed MASK ROM with short turn around time in programming processes, and small cell size is descrived. The memory cell is implemented by NOR gate type which is most suitable for high speed MASK ROM. The new memory cell is successfully applied to 1Mbit MASK ROM with double polysilicon P-well C-MOS technology. A new structure and a new fabrication processes of the device element are also described.

A double-diffused MNOS transistor as a new non-volatile memory

A new device structure for MNOS non-volatile memory is proposed for the purpose of getting higher writing speed and lower writing voltage. Basic concept is quite analogous to the double-diffused MOS transistor, where the gate oxide is replaced by a combination of the ultrathin oxide of silicon and the silicon nitride. When operated by the hybridization mode of the direct tunneling and the avalanche injection, typical results are as follows: (a) writing time is reduced to less than 100 ns, and (b) writing voltage is about 25 volts which is 10 volts lower than the conventional MNOS structure with the same nitride and oxide thicknesses of 400 A and 16.5 A respectively.

N-Channel MNOS EAROM for TV Electronic Tuning System

A new n-channel MNOS technology for EAROM applications has been developed by introducing a threshold voltage control technique. The technology is principally based on a low energy implantation of boron ions for obtaining a positive center voltage in the threshold window, which results in better retentivity. By incorporating this MNOS technology and n-well CMOS technology on an isolated epitaxial layer, an n-channel MNOS EAROM is fabricated for TV electronic tuning system. The EAROM utilizes the two MNOS transistors per cell configuration. The device showed a long data retention time over 10 years at 80 °C after 105 erasing/writing cycles, therefore the technology appears to be quite promising for EAROM applications.

A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors

A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as a non-volatile memory with data retentivity of about one year. Nonvolatile writing to the MNOS transistors is done only when the power supply is turned off and on. The allowable number of on/off cycles can exceed 105 cycles under normal operating conditions. Power dissipation as a static RAM is less than 600 mW and that as a nonvolatile memory is zero. Both inputs and outputs are TTL compatible except for the signal to the gate of MNOS transistors.