Philip J. Tobin

Thermodynamic stability of high-K dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2

We present theoretical and experimental results regarding the thermodynamic stability of the high-k dielectrics ZrO2 and HfO2 in contact with Si and SiO2. The HfO2/Si interface is found to be stable with respect to formation of silicides whereas the ZrO2/Si interface is not. The metal–oxide/SiO2 interface is marginally unstable with respect to formation of silicates. Cross-sectional transmission electron micrographs expose formation of nodules, identified as silicides, across the polycrystalline silicon/ZrO2/Si interfaces but not for the interfaces with HfO2. For both ZrO2 and HfO2, the x-ray photoemission spectra illustrate formation of silicate-like compounds in the MO2/SiO2 interface.

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Contributions to the effective work function of platinum on hafnium dioxide

The intrinsic and extrinsic contributions to Fermi level pinning of platinum (Pt) electrodes on hafnium dioxide (HfO2) gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the effective work function of Pt-HfO2-silicon capacitors. The effective platinum work function is ∼4.6eV when annealed in forming gas. However, diffusion of oxygen to the Pt∕HfO2 interface increases the platinum work function to a value of ∼4.9eV. Subsequent annealing in forming gas returns the platinum work function to a value comparable to that measured prior to the oxygen anneal. The effective platinum work functions are compared to the prediction of the metal induced gap states (MIGS) model. The presence of interfacial oxygen vacancies or platinum–hafnium bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone.

Furnace formation of silicon oxynitride thin dielectrics in nitrous oxide (N2O): The role of nitric oxide (NO)

We have studied the growth kinetics of the N2O furnace oxynitridation process demonstrating the importance of input flow rate, and therefore gas residence time, in determining the final film thickness and the nitrogen concentration. This dependence on residence time can explain the variation in the tendency to thickness saturation observed in the film growth data reported by several groups. Using published gas phase kinetic data, we have shown that, for a 950 °C oxynitridation process, N2O decomposes into N2, O2, and NO before reaching the wafer load. Again using published information, we have derived a simple equation which describes the subsequent reaction between NO and O2 to produce NO2 as the gas flows down the tube. This reaction results in loss of NO by an amount which depends on the gas residence time and therefore on the input gas flow rate and the dimensions of the system. Since it can be argued that NO2 does not contribute to nitridation, this system‐dependent loss of NO can explain the variation in the reported film growth data. Combining our experimental data and model, we find that the peak nitrogen concentration in the film depends linearly on the NO gas phase concentration. Further, the oxynitride grows more slowly as the NO concentration increases supporting the idea that oxidation sites are blocked by nitrogen as oxynitridation time increases.

Growth and surface chemistry of oxynitride gate dielectric using nitric oxide

Oxynitride films grown on preoxidized (100) silicon surfaces in a nitric oxide (NO) ambient at 950 °C have been investigated using x‐ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), and cross‐sectional transmission electron microscopy (XTEM). Compared to N2O oxynitride, NO oxynitride exhibits very different surface chemistry, interface properties, and growth mechanisms. The etch back of NO and N2O oxynitride films allows control of sample thickness for the XPS measurements. NO oxynitride has the interfacial nitrogen (Nint) sharply peaked on the Si substrate side of the interface, while it is broad and on the dielectric side of the interface for the N2O oxynitride. The N(1s) XPS results reveal a clear distinction between N2O oxynitride and NO oxynitride. Near the Si/dielectric interface the NO oxynitride shows primarily Si≡N bonds, while the N2O films showed a N(1s) binding energy peak that is in‐between that of Si≡N bonds and Si2=N—O bonds. Furth...

Fermi level pinning at the polySi/metal oxide interface

We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-k) gate oxide. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled to 10 A equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other gate stack scaling concerns like boron penetration and elevated gate resistance. Extensive simulations have shown that the optimal gate work functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-type MOSFETs (p-type MOSFETs). This study summarizes the evaluations of TiN, Ta–Si–N, WN, TaN, TaSi, Ir, and IrO2 as candidate metals for dual-metal gate complementary metal–oxide semiconductor using HfO2 as the gate dielectric. The gate work function was determined ...

Impact of Deposition and Annealing Temperature on Material and Electrical Characteristics of ALD HfO2

Hafnium oxide (HfO 2 ) is one of the most promising high-k materials to replace SiO 2 as a gate dielectric. Here we report material and electrical characterization of atomic layer deposition (ALD) hafnium oxide and the correlations between the results. The HfO2 films were deposited at 200, 300, or 370°C and annealed in a nitrogen ambient at 550, 800, and 900°C. Results indicate that deposition temperature controls both the material and the electrical properties. Materials and electrical properties of films deposited at 200°C are most affected by annealing conditions compared to films deposited at higher temperatures. These films are amorphous as deposited and become polycrystalline after 800°C anneals. Voids are observed after a 900°C anneal for the 200°C deposited films. The 200°C deposited films have charge trapping and high leakage current following anneals at 900°C. The 300°C deposited films have lower chlorine content and remain void-free following high-temperature anneals. These films show a thickness-dependent crystal structure. Annealing the films reduces leakage current by four orders of magnitude. Finally, films deposited at 370°C have the highest density, contain the least amount of impurities, and contain more of the monoclinic phase of HfO 2 than those deposited at 300 and 200°C. The best electrical performance was obtained for films deposited at 370°C.

Challenges for the integration of metal gate electrodes

Integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed. Gate stack thermal instabilities are explored, and for the first time results using tantalum-carbon based electrodes are presented.