Jeffrey D. Black

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

RHBD techniques for mitigating effects of single-event hits using guard-gates

Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hits are presented. Simulation results show that the designs using guard-gates are less susceptible to single-event hits. Area, power, and speed penalty for guard-gate designs for combinational logic are found to be minimal. For latches, the area penalty is higher but speed penalty is minimal.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate of SETs longer than 1 ns.

Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAMs state is shown to be based upon the resistive path from the p+ -sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.

Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

Heavy Ion Testing and Single Event Upset Rate Prediction Considerations for a DICE Flip-Flop

Monte-Carlo simulation using the MRED software suite, coupled with SPICE analysis, is used to identify internal mechanisms of SEU in DICE flip-flops. Low frequency cross-section measurements and simulations identify multiple-node charge collection SEU mechanisms as the dominant contributor. An increasingly isotropic response is predicted with increasing frequency due to latching of internal single-node transients near clock boundaries. Implications for heavy ion testing and SEU rate prediction are presented.