S. Brus

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI

This report discusses a new and practical approach to implement low Vt bulk CMOS using Ni-based FUSI MOSFETs. On the nFET, we demonstrate for the first time that incorporating Yb by ion implantation can achieve similar reduction of effective work function (WF) compared to alloying making it a candidate for CMOS integration. We complement our previous work on WF modulation by Yb on NiSi/SiON with new data on NiSi/HfSiON and NiGeSi/HfSiON. On the pFET, we study the effect of Al and Pt on Ni-rich FUSI and integrate it with a SiGe-channel. Integration into our reference devices resulted in a Vt reduction from 0.55/0.61V down to 0.30/0.25V for nFET (NiSi:Yb gate) and pFET (Ni2 Si:Pt gate + SiGe channel) respectively on SiON without degradation of the dielectric integrity and long channel mobility, and without an increase in gate leakage and Dit

FinFETs Junctions Optimization by Conventional Ion Implantation for (Sub-)22nm Technology Nodes Circuit Applications

In this work we explore several doping schemes for aggressively scaled FinFET devices (HFin~37nm, WFin≥10nm, Lg≥30nm), using conventional ion implantation, and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, singlesided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher 6T-SRAM SNM values. Key advantages of the extension-less approach are: reduced cost & cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Siepitaxial raised S/D (SEG), and up to 20× lower IOFF. It, however, requires a tight spacer CD control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins. Introduction FinFET-based multi-gate (MuGFET) devices are considered one of the most promising device architectures for enabling further CMOS scaling beyond the 32nm technology node, thanks to their improved electrostatics and steeper sub-threshold slopes, with reduced VT variability due to lower channel dopants concentration [1-8]. This makes them particularly attractive for helping prolong SRAM scaling, facing ever-increasingly challenges with maintaining acceptable noise margins and controlled instability. However, FinFET parasitics remain a concern, requiring reduction of the series resistance RSD through improved Fin morphology and Fin doping [5,9]. For ion implanted junctions, this issue is greatly aggravated by tilt angle restrictions due to resist shadowing in tight pitch structures. Recently, to reduce non-uniformity of implanted dosage in the Fins in an SRAM cell, responsible for characteristic variability degradation, a single-sided I/I scheme was proposed, reporting stable SRAM operation, but lower drive current compared to the double-sided I/I case due to higher extension resistance [4]. In this paper, using conventional ion implantation, several doping strategies for highly scaled FinFET devices are evaluated for improved variability control at denser pitches, with no penalty in performance, leakage nor Short-Channel-Effects (SCE), and with demonstrated scalability for (sub-)22nm circuits (RO and SRAM). Device fabrication A schematic of the process flow used for device fabrication is shown in Fig.1, starting with SOI thinning down to ~40nm to allow a more robust gate patterning process at scaled pitches. A corner rounding step to remove etch-induced Si damage and smoothen the Fin sidewalls follows Fin patterning (WFin≥10nm). HfSiON/TiN gate stack, capped with a-Si and CET~2.2nm, is patterned using an oxide/α-C/SiOC hard-mask (HM). Extensions I/I were preceded by a thin oxide liner deposition, at 200°C, to reduce dose loss during strip. Extension-less devices were fabricated with a narrower 1 (HDD) spacer (CD≤12nm after SEG) and thinner, ~23nm-thick SEG (Fig.2). With addition of a 2 spacer, total spacer width prior to silicidation is similar for all devices. Device characteristics and Circuits results Fig.3 illustrates the two implant options considered for dense Fin pitches to avoid shadowing effects: a) low-tilt, double-sided I/I and b) high-tilt, single-sided I/I. Extension-less devices using the 1 approach (low-tilt, 2Q HDD I/I) were also investigated, starting with simulations vs. reference devices (Fig.4) for assessing the impact of several process parameters changes, such as spacer width variations, in junctions profile and device characteristics. RSD extracted for NMOS and PMOS devices, at relaxed pitch, for the different I/I options are shown in Fig.5. With optimized I/I conditions, no resistance penalty is obtained for singlevs. doublesided extension I/I. As for the extension-less devices, the better quality, defect-free SEG obtained when starting from undoped Fins [8,9] means that low RSD values can be obtained with thinner SEG, with margin for further improvement by increasing its growth time, and potentially resulting in less Rout variability [5]. Regarding device performance, Fig.6 shows that optimized extension-less devices exhibit lower IOFF values, consistent with the expected reduced gate overlap, also controlled to avoid high increase in RSD. Excellent SCE behavior is obtained (Fig.7), corresponding to comparable (PMOS) or even slightly higher performance in NMOS devices: ~8% drive current increase at fixed IOFF=100nA/μm (Fig.8). An overview of the ITP characteristics of PMOS devices fabricated with the different doping schemes is shown in Fig.9. Comparable performance can be obtained with (B 0.8keV) singlesided, 25° tilt extension I/I vs. double-sided, 45° tilt extension I/I, compensating the dopant loss at lower I/I angles with a small dose adjustment. These asymmetrically doped PMOS devices also outperform low-tilt I/I devices in about ~7-10% higher ION at IOFF=100nA/μm. The ID-VG curves in Fig.10 (NMOS devices for different doping strategies) highlight again the lower off-state current of extension-less devices vs. the other implant strategies, corresponding to a lower DIBL~36mV/V and SS~70mV/dec. Fig.11 shows that for both NMOS and PMOS devices, tight VT distributions (σ(VTlin)≤20mV) can be obtained for the different I/I schemes (data at relaxed pitch, without shadowing effects impact). Implementation into Ring Oscillators (Fig.12; data shown for ROs with 12 and 16 Fins for NMOS and PMOS devices, respectively) shows that comparable performance can be obtained for singlevs. double-sided, high-tilt extension I/I devices with optimization of the implant conditions. On the other hand, lower static power dissipation is obtained for low-tilt I/I devices. In agreement with the tight distributions in Fig.11, comparable VT-mismatch results (σ(ΔVT)≤30mV) are shown in Fig.13 for aggressively scaled Pull-Down (PD), Pass-Gate (PG) and Pull-Up (PU) transistors of relaxed SRAM cell sizes, for the different doping schemes. This is, of course, due to the fact that, in this case, shadowing effects are of no concern. However, the correspondent cells SNM values shown in Fig.14 are clearly higher for the lowtilt I/I and high-tilt, single-sided extension I/I schemes, the most suitable doping approaches for scaled, denser cells. Improved operating margin can also be achieved by increasing the cell β ratio from 1 to 1.7, through an increase in the gate length for the PG transistor, as shown in Fig.14 (right plot). Overall, successful SRAM operation requires good SCE, low leakage, and a robust contact module. The extension-less approach, exhibiting lower offstate current, while keeping low RSD, can then be particularly attractive for scaled cells. Butterfly curves of a 22nm node 6TSRAM cell (0.099μm cell size [8]) successfully built up with this approach are shown in Fig.15, with SNM>0.1VDD down to 0.6V. Conclusions This work demonstrated a junctions formation methodology for aggressively scaled FinFET devices, using conventional ion implantation, and compatible with dense pitches applications, without penalty in RSD nor device performance, and yielding higher SRAM SNM values: 1) low-energy & low-tilt, double-sided extension(-less) I/I approach, with key advantages in terms of cost & cycle time, better quality, defect-free SEG, and lower IOFF when skipping extensions; or 2) low-energy & high-tilt, single-sided extension I/I scheme, less sensitive to resist profile and allowing wider overlay margins (higher scalability), with the design constrain of needing to account for isolated/dense differences. References [1] J. Kavalieros et al., VLSI Tech. Dig. 2006, 62; [2] S. Inaba et al., IEDM Tech. Dig. 2007, 487; [3] N. Collaert et al., ICICDT Tech. Dig. 2008, 59; [4] H. Kawasaki et al., IEDM Tech. Dig. 2008, 237; [5] T. Mérelle et al., IEDM Tech. Dig. 2008, 241; [6] A. Veloso et al., IEDM Tech. Dig. 2008, 861; [7] C.-Y. Chang et al., IEDM Tech. Dig. 2009, 293; [8] A. Veloso et al., IEDM Tech. Dig. 2009, 301; [9] R. Duffy et al., Appl. Phys. Lett. 90, 241912, 2007. -1024Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp1024-1025 C-7-4

Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer

Abstract MoON has been reported to be a good PMOS candidate. In this paper, we report tuning of the MoON PMOS metal towards Si conduction band-edge with Vtau as low as 0.35V for SiON capped with DyO, using a standard high temperature gate first process flow. Consistent shifts of 450 mV in VFB and Vtau are observed by capping SiON with DyO for MoON gate. Gate leakage as low as 10-7 A/cm2 at 17.6A EOT is obtained, outperforming HfSiON by 3 orders of magnitude. Intermixing of SiON and DyO is shown to be the key element leading to low EOT and low gate leakage without any degradation of the gate oxide integrity.

Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.

Devices with High-k Last Replacement Metal Gate Technology A. Veloso, S. A. Chew, Y. Higuchi, L.-Å. Ragnarsson, E. Simoen, T. Schram, T. Witters, A. Van Ammel, H. Dekkers, H. Tielens, K. Devriendt, N. Heylen, F. Sebaai, S. Brus, P. Favia, J. Geypen, H. Bender, A. Phatak, M. S. Chen, X. Lu, S. Ganguli, Y. Lei, W. Tang, X. Fu, S. Gandikota, A. Noori, A. Brand, N. Yoshida, A. Thean, and N. Horiguchi IMEC, assignee at IMEC from Panasonic, Applied Materials Belgium NV, Kapeldreef 75, 3001 Leuven, Belgium; Applied Materials Inc., 3050 Bowers Ave., Santa Clara, CA 95054, USA Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

FinFETs and Their Futures

FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production, quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.

Achieving low V T Ni-FUSI CMOS via lanthanide incorporation in the gate stack

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (JG) reduction; 2) adding a cap has no significant impact on Tinv (<1Aring), while up to ~5 and 2 A reduction occurs for SiON and HfSiON Yb-implanted devices, respectively; 3) the largest JG reduction (150 x) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500 mV smaller VT; 4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; 5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both WF tuning methods. They allow DeltaWF(n-p) values up to ~800 meV when combined with Ni-silicide FUSI phase engineering, promising for low-VT CMOS.