T. Hoffmann

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

Review of FINFET technology

Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FINFET devices. The high performance sensitivity to fin dimensions (width, height, LER) sets up very tight restrictions for the process control which may create a big challenge to demonstrate process manufacturability.

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400cm2/eV-s and 1300cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high performance CMOS applications with an emphasis on progressive EOT scaling.

GaSb molecular beam epitaxial growth on p-InP(001) and passivation with in situ deposited Al2O3 gate oxide

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III–V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-κ gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C–V with relatively low Dit along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface.

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

A novel silicide formation technique using milli-second anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6nm gate length reduction and more than 1 decade junction leakage imporvement.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

\hbox{Ni}_{2}\hbox{Si}

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

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The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni₂Si, and Ni₃₁Si₁₂. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V_t control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni₂Si processes with excessive thermal budgets, resulting in significant V_t shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V_t rolloff characteristics was demonstrated for NiSi, Ni₂Si, and Ni₃₁Si₁₂ FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni₂Si are less than or equal to 25 degC, whereas a single-phase Ni₃₁Si₁₂ is obtained over an ~200degC temperature range

\hbox{Ni}_{31}\hbox{Si}_{12}

The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (Tinv) as a result of stronger charge and surface roughness scattering at thinner SiOx interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at Tinv=12.5Å. In the UTBOX-FDSOI device architecture, a positive back gate bias provides a strong enhancement in electron mobility. In SiGe-QW pFET devices, a 150% improvement in hole-mobility is observed with low thermal budget laser-anneal (LA).