P. Fernández-Martínez

Radiation effects in Low Gain Avalanche Detectors after hadron irradiations

Novel silicon detectors with charge gain were designed (Low Gain Avalanche Detectors - LGAD) to be used in particle physics experiments, medical and timing applications. They are based on a n++-p+-p structure where appropriate doping of multiplication layer (p^+) is needed to achieve high fields and impact ionization. Several wafers were processed with different junction parameters resulting in gains of up to 16 at high voltages. In order to study radiation hardness of LGAD, which is one of key requirements for future high energy experiments, several sets of diodes were irradiated with reactor neutrons, 192 MeV pions and 800 MeV protons to the equivalent fluences of up to Φeq=1016 cm−2. Transient Current Technique and charge collection measurements with LHC speed electronics were employed to characterize the detectors. It was found that the gain decreases with irradiation, which was attributed to effective acceptor removal in the multiplication layer. Other important aspects of operation of irradiated detectors such as leakage current and noise in the presence of charge multiplication were also investigated.

The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate–drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.

Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (Ron) value maintaining the same voltage capability. The increment of the N+ source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate–drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate–oxide degradation by hot carriers.

Simulation of Total Ionising Dose in MOS capacitors

Total Ionising Dose (TID) effects are the most important effects of ionising radiation in MOS devices. Among others, TID cause charge trapping in the oxide and in the oxide-semiconductor interface. In this work we develop physical simulation models of charge trapping TID effects in MOS capacitors, in order to have a calculation model for postirradiation experiments. Simulations are made using the Sentaurus TCAD suite, comparing results with well established literature. We calculate the modifications in the C-V curve and the dependence of the flat band voltage due to charge trapping in the oxide, interface traps and the combination of both for increasing dose.

Design and fabrication of an optimum peripheral region for low gain avalanche detectors

Abstract Low Gain Avalanche Detectors (LGAD) represent a remarkable advance in high energy particle detection, since they provide a moderate increase (gain ~10) of the collected charge, thus leading to a notable improvement of the signal-to-noise ratio, which largely extends the possible application of Silicon detectors beyond their present working field. The optimum detection performance requires a careful implementation of the multiplication junction, in order to obtain the desired gain on the read out signal, but also a proper design of the edge termination and the peripheral region, which prevents the LGAD detectors from premature breakdown and large leakage current. This work deals with the critical technological aspects required to optimize the LGAD structure. The impact of several design strategies for the device periphery is evaluated with the aid of TCAD simulations, and compared with the experimental results obtained from the first LGAD prototypes fabricated at the IMB-CNM clean room. Solutions for the peripheral region improvement are also provided.

Rad-hard vertical JFET switch for the HV-MUX system of the ATLAS upgrade Inner Tracker

This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as switches for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET transistor. As these devices are expected to operate under very high radiation conditions during the whole experiment life-time, a study of the radiation damage effects and the expected degradation on the device performance is also presented at the end of the paper.

Gain estimation of RT-APD devices by means of TCAD numerical simulations

The design of Reach-Through Avalanche Photodiodes (RT-APD) for medium energy X-ray detection requires a previous optimization to guarantee elevated gain at the required operation conditions. A simple methodology to estimate the gain in RT-APD devices by using TCAD numerical simulations is proposed in this work. This technique offers the possibility to predict the gain in RT-APDs as a function of the most relevant design considerations.

Simulation methodology for dose effects in lateral DMOS transistors

Due to the increasing interest on laterally diffused MOS (LDMOS) transistors as a part of power electronics in the high energy physics (HEP) experiments, the effect of total ionising dose (TID) on their electrical performances has been experimentally measured. The analysis of the experimental results requires the aid of physics-based simulations to study the impact of TID effects on the LDMOS drift oxide layer. In this work, a simulation methodology is developed in order to analyse the changes in the electric field distribution as a consequence of the TID induced trapped charge, and its relationship with the technological parameters and the bias conditions. The simulation results are compared with the experimental data.

GaN Ohmic contact resistance vs temperature

The temperature impact on the Ohmic contact to Gallium Nitride (GaN) device properties is investigated in the range of 25°C to 300°C by means of the Transmission Line Method (TLM) technique. This study is centered in two kinds of Ohmic contacts: Implanted N+ GaN and heterojunction AlGaN/GaN contacts. For N+ contact resistance behavior is explained in terms of the field-effect or thermionic field effect current transport mechanism. However, the heterojunction contact resistance behavior is explained by the mobility properties in the two dimensional electron gas.