P. Mora

HCI/BTI coupled model: The path for accurate and predictive reliability simulations

The standard qualification of CMOS Wafer Level Reliability by manufacturers consists in qualifying BTI mechanism from one side and HCI from another side independently. Their respective degradation are then assumed to be additive. Here, we study the interaction between both mechanisms through alternative stress sequences at device level and also in ring oscillators. Interaction formalism is proposed and implemented in Design-in-Reliability simulation framework. While two ageing mechanisms co-exist and are interacting, we consider the origin of mechanisms (non-conducting HCI, low-E HCI...) and quantify the weight of coupling. We also point out that without this interaction consideration in Design-in-Reliability simulation, results are significantly inaccurate and pessimistic. Finally, we present degradation results for a large amount of standard cell RO-based at package level, at different stress/time conditions and conclude that this feature of simulation is a must have in logic Design Platform characterization in order to avoid over-estimation of timing degradation.

Energy-driven Hot-Carrier model in advanced nodes

With technology scaling, highly integrated devices have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injections (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper an experimental analysis of HCI degradation for fully depleted Silicon On Insulator (FDSOI) MOSFETs. The carrier energy and bulk bias dependencies are modeled according to our recent findings through a simple HC model based on physical theories applied to the specificity of FDSOI technology with body bias operation.

Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes

We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.

Hot-Carrier Injection Degradation in Advanced CMOS Nodes: A Bottom-Up Approach to Circuit and System Reliability

The development of most applications in the microelectronics industry is driven by an increase in the working frequency. Each product can be used under various types of mission profiles, thus forcing a large variety of signal types on each transistor. One growing concern involves the capability to guarantee the working frequency not only of a fresh product, but after years of operation. As a consequence, accurately characterizing the reliability at a transistor level became mandatory, with the necessity to consider various stress conditions and the obligation to achieve a good prediction capability. In this context, the degradation of the transistor under hot-carrier injection (HCI) degradation stress can no longer be studied at the so-called worst-case stress condition [1] but must cover all V gs/V ds working conditions [2]. The study of new stress conditions has evidenced new degradation phenomena [such as electron–electron scattering (EES) or multiple vibrational excitation (MVE)]. Their nontrivial understanding [2–4] requires analyzing the degradation at a microscopic scale in order to come up with predictive modeling at a transistor level and even higher hierarchical modeling levels.

Reliability issues related to Fast Charge Loss Mechanism in Embedded Non Volatile Memories

In this work, we report on a thorough study of charge loss in embedded non volatile memories. We focused on the fast initial threshold voltage (Vth) shift, which occurs during the first minutes of data retention bake. Experiments were performed to have a better understanding of this phenomenon. As a result, we can predict the Vth shift of a cell baked at 250degC and evaluate its impact on product reliability. This is the first time that this reliability aspect is characterized with such a level of accuracy. Based on these observations, a physical model is proposed to describe the fast initial threshold voltage shift

28nm UTBB FDSOI product reliability/performance trade-off optimization through body bias operation

This paper demonstrates the tremendous advantage of body biasing to set the best reliability/performance trade-off of electronic products. First, we review experiments performed on transistors, ring oscillators (RO) and CPU to quantify the impact of body biasing on reliability and performances. Then, the full picture including power, speed and reliability is discussed to highlight the way to get optimized circuits for different activities. Finally, we show that a unique dynamic management of performance and reliability can be achieved through body biasing operation.

Frequency dependence of TDDB & PBTI with OTF monitoring methodology in high-k/metal gate stacks

This paper deals with AC/DC effect on nMOS TDDB (Time Dependent Dielectric Breakdown) and PBTI (Positive Bias Temperature Instability) using suitable OTF (on the Fly) monitoring methodologies. First, an adapted unipolar AC stress without stress interruption is used to study TDDB dependences on frequency and duty cycle. For frequencies above 100Hz, Time to Breakdown is shown to depend significantly on these two parameters. On the other hand, in order to evidence a possible effect of trapping on TDDB, PBTI dependences on frequency and duty cycle are also studied using fast BTI measurement. Finally, trapping/detrapping mechanisms fail to explain TDDB observations.

Modeling of hot carrier injection across technology scaling

Hot carrier Injection mechanism is an important reliability concern of CMOS devices. While the critical gate dimension length is scaled down, this mechanism of degradation is exacerbated due to the increase of the local electrical field. For different planar and FinFET of N-channel MOS technology nodes, the scalability of this mechanism is presented and discussed. The underlying physical mechanism involved in HCI condition is reviewed and discussed. Stress renormalization through age rate function for several technology nodes is presented. At circuit level, predictive simulation can be handled with Design-for-Reliability framework. Interactions between degradation mechanisms involved in HCI are accounted in the simulation.

Application of compact HCI model to prediction of process effect in 28FDSOI technology

A comprehensive study of HC reliability and process change variation for submicron fully depleted Silicon On Insulator (FDSOI) MOSFETs is presented. The different process variation within the FDSOI technology and their impact on HC degradation are examined (i.e. channel length L, Source/Drain resistance RSD, oxide thickness Tox, lightly-doped drain LDD). In order to prove its consistence, our energy driven model recently presented will be applied to the different process changes.

A self heating test structure using poly resistors and P/sup +//N diodes to characterize anomalous charge transfers in embedded flash memories

We report on the characterization of a self heating test structure which allows the monitoring of charge loss or gain of embedded flash memories with a high level of time accuracy. A calibration of the test structure has been successfully performed between 25/spl deg/C and 300/spl deg/C. Furthermore, voltage and current operating points were determined in order to obtain the self heating structure temperature profile needed for charge transfer studies. Finally, data retention results of flash memories were presented to validate the operating of the structure. Considering the results, the monitoring of charge transfers appears as a powerful application.