Paolo Ghezzi

Modeling of the intrinsic retention characteristics of FLOTOX EEPROM cells under elevated temperature conditions

A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells. >

Accelerated current test for fast tunnel oxide evaluation (of EPROMs)

An accelerated method for wafer-level tunnel oxide evaluation and screening is proposed and compared to the widely used constant current test. The dielectric is stressed by an exponentially increasing current flow until breakdown occurs. In a short measurement time a wide current density range is explored, so that both latent defectivity and intrinsic oxide properties can be monitored. It is concluded that sensitivity in charge to breakdown determination and its good correlation with constant current stress results make the ramped current method suitable for routine use in both R&D and production.<<ETX>>

Wafer level tunnel oxide reliability evaluation by means of the Exponentially Ramped Current Stress method

Abstract The Exponentially Ramped Current Stress method (ERCS) is an accelerated test for wafer-level tunnel oxide evaluation and screening. In this work the technique is described and its advantages are discussed, with special attention to the comparison with the most widely used constant current test. In the ERCS the dielectric is stressed by an exponentially increasing current flow until breakdown occurs. In a short measurement time a wide current density range is explored, so that both defectivity and intrinsic oxide properties can be monitored. The intrinsic charge-to-breakdown dependence on capacitor area and on current density under constant current stress have also been investigated, both for gate and for substrate charge injection. A simple algorithm is proposed in order to correlate the two techniques, allowing for the projection of the results obtained with the ERCS method to constant current stress conditions. The self-consistency of such an algorithm has been verified on the base of independent experimental results. It is concluded that the Exponentially Ramped Current Stress is suitable both as an efficient tool in Research and Development and as a routine control in production; in fact, the method shows several desirable qualities, such as the short measurement time, the good sensitivity in charge to breakdown determination over a wide range, the good correlation with constant current stress results, as well as the possibility of other electrical parameter extraction (i.e. Fowler-Nordheim characteristics, breakdown electric field, Time Dependent Dielectric Breakdown).

A study of the oxide grown on WSi2

Modern single-poly electrically erasable programmable read-only memories (EEPROM) use a stacked silicide/polysilicon (polycide) floating gate as a charge storage element. In these devices the ability to retain stored charge relies on the quality of the top silicon dioxide, thermally grown on the silicide, which is known to be affected by the oxidation procedure. The authors have studied silicon dioxide films, thermally grown in a dry oxygen atmosphere on WSi2, both in terms of composition and electrical properties. Concentration depth profiles were obtained by means of Auger electron spectroscopy (AES), while electrical characteristics were obtained on poly-Si/SiO2/WSi2 capacitors, from C-V plots, I-V measurements and ramped voltage stress. To characterize the oxide reliability, the endurance and memory retention at high temperature have been measured on single-poly EEPROM cells. The results show that the oxide thermally grown on tungsten silicide can meet the requirements for single-poly PROM device fabrication. The functionality of memory cells has been demonstrated, both with endurance and retention measurements.

On the endurance performance of FLOTOX EEPROM cells with WSi2 overcoated floating gate electrode

Abstract Comparison between endurance performance obtained on FLOTOX EEPROM cells with heavily doped poly-Si as floating gate electrode and heavily doped poly-Si overcoated with WSi 2 is presented. The poor endurance performance which has been obtained on the memory cells with silicidated floating gate electrodes has been quantitatively attributed to fluorine contamination of the tunnel oxide layer, introduced during the LPCVD silicide deposition process step. Finally, the necessity for optimizing the post-silicidation annealing procedure is proposed.

Impact of reactive ion etching using O/sub 2/+CHF/sub 3/ plasma on the endurance performance of FLOTOX EEPROM cells

The influence of the reactive ion etching (RIE) process step performed with O/sub 2/+CHF/sub 3/ plasma on the endurance performance of FLOTOX EEPROM cells is investigated. The comparison with the standard wet etching procedure (WEP) shows that the observed higher programming window degradation Delta W/sub p/ as well as the unbalanced high-to-low state threshold-voltage shifts can be quantitatively attributed to the fluorine (F) contamination of the tunnel oxide layer near the floating gate (FG) electrode. >

Programming Window Degradation in Flotox Eeprom Cells

A theoretical model explaining the programming window degradation as a function of the number of Write/Erase cycles in FLOTOX EEPROM cells is proposed. The collapsing of the programming window is quantitatively related to the oxide charge build-up in the FLOTOX tunnel region as the cycling number increases. The simplicity of the model permits a direct application at CAD level to be expected.

Advanced salicided 4 Mbit flash memory array with borderless contacts

System on chip development requires many different devices to be integrated on the same chip and a high compatibility between CMOS logic core process and added modules. The self-aligned silicide process coming from high performance logic gives in a Flash memory array several opportunities: to take advantage of low word-line resistance, to eliminate any metal strap in the array reducing potential process defectivity thus improving devices yield. On the other hand, the salicidation of Flash memory requires at the same time to achieve a continuous low resistance line on the no-flat array topography (due to the double poly stacked gate memory cell structure) and to avoid any junction leakage risk, that might modify the device performances. The aim of this work is to demonstrate the feasibility and compatibility of advanced Ti salicide process with Flash memory array embedded in a high performance logic. The feasibility has been proven on a classical NOR 4 Mbit stand-alone memory test chip processed in 0.25 μm technology, that furthermore asks for borderless contacts.