Paolo Valerio Testa

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier

This paper presents a travelling-wave amplifier (TWA) for wideband applications implemented in a 0.13 µm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). The gain cell employed in the TWA is designed to compensate the transmission-line- losses at high frequencies in order to extend the bandwidth as well as the gain bandwidth product (GBP). A gain of 10 dB and a 3-dB bandwidth of 170 GHz are measured for the fabricated TWA. The chip has a chip area of 0.38 mm² and a power consumption of 108 mW. Compared against the state of the art, the presented design achieves the highest reported GBP per area and power consumption.

220 GHz wideband distributed active power combiner

This paper presents an active power combiner for UWB applications implemented in a 0.13 μm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). The circuit is based on distributed architectures: two travelling wave amplifiers sharing the output line are used for the signal combining, whereas a cascade single-stage distributed amplifier ensures high gains for the combining paths. The 3 dB bandwidth of operation is demonstrated from 1 to 170 GHz, while the 6 dB upper frequency exceeds 220 GHz. Good performances in terms of group delay variation are also reported. Over the 3 dB bandwidth the group delay variation is less than 10 ps, and over the 6 dB one it is less than 15 ps. The signal amplification in each path of the combiner is 20 dB from 1 to 170 GHz and it decreases to 15 dB at 220 GHz. Independent bias networks for each combining path enable also selective gain tuning capabilities: a gain tuning range of 20 dB is demonstrated. The system requires a chip area of 0.57 mm2 and 203 mW of DC power. Compared against the state of the art, the presented circuit offers the widest bandwidth as well as the highest combining path gain.

Distributed on-chip antennas to increase system bandwidth at 180 GHz

This paper presents integrated, distributed on-chip antennas. The aim is to achieve a higher system bandwidth due to the utilization of multiple antennas and the combining of their frequency ranges. All designs will be manufactured in the 130nm IHP SG13G2 process. Furthermore the measurement setup is described and measurement results are shown.

180 GHz low-power bandwidth-enhanced BiCMOS cascaded single-stage distributed amplifier

This paper presents a four-stage cascaded single-stage distributed amplifier (CSSDA) for wideband and low power applications implemented in a 0.13 μm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). A 3 dB upper frequency of 180 GHz, a bandwidth of 130 GHz, and a gain of 9.5 dB are measured for the fabricated CSSDA. The circuit requires a chip area of 0.28 mm2 and only 19.5 mW of dc power consumption. To enhance the amplifier gain and bandwidth without increasing the dissipated power, innovative peaking techniques have been employed. Compared against the state of the art, the presented design solution offers the lowest power consumption and the smallest occupied area, without sacrificing excessively speed, gain and gain-bandwidth product.

250 GHz SiGe-BiCMOS Cascaded Single-Stage Distributed Amplifier

This paper presents a cascaded single-stage distributed amplifier (CSSDA) for wideband applications implemented in a 0.13 μm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). A 3 dB upper frequency of 250 GHz, a bandwidth of 170 GHz, and a gain of 13 dB are demonstrated for the fabricated CSSDA. The circuit requires a chip area of 0.23 mm2 and 74 mW of DC power. Compared against the state of the art, the presented design achieves the highest speed and the smallest area.

Analysis and Design of a 220-GHz Wideband SiGe BiCMOS Distributed Active Combiner

This paper presents the first active power combiner designed for ultrawideband applications covering a bandwidth of operation from 1 to 220 GHz. The circuit is implemented in a high-performance 0.13-μm SiGe BiCMOS technology (fmax = 450 GHz) and based on an innovative dual-stage distributed architecture. The input stage realizes the power combination with a traveling-wave architecture. The output stage is a cascaded single-stage distributed amplifier, and it is employed to increase the overall gain. The circuit analysis necessary for circuit design is given, and its predictions are compared with the measurements in the time and frequency domains. The system requires 203 mW of dc power to provide a signal amplification of 20 dB from 1 to 170 GHz, which decreases to 15 dB at 220 GHz. Independent bias networks for the combining paths also enable a gain tuning range of 20 dB. The presented circuit improves by a factor 16 the state of the art for frequency of operation of distributed power combiners implemented in silicon and by a factor 20 the bandwidth. Compared with III-V implementations, the improvement factors are 4.5 and 5.5, respectively.

Gain-bandwidth tuning techniques for loss-compensated Travelling Wave Amplifiers

This paper presents gain and bandwidth control techniques for wideband loss-compensated Travelling Wave Amplifier (TWAs). The behavior of the distributed amplifiers is tuned acting on the circuit bias in two ways: changing the transistor operation points from saturation to forward active, and tuning the amplifier loss compensation. A tuning range for the gain of 40 dB has been experimentally validated on an existing 0.13 μm SiGe BiCMOS TWA. During the gain tuning the group delay and input and output return losses showed almost no variations over the 170 GHz amplifier bandwidth. Moreover, the presented techniques enabled the control of the upper 3 dB corner frequency. The presented results compare well against the state of the art for variable gain distributed amplifiers (VGDAs) with outstanding bandwidth of operation and gain tuning range.

0.5–20 GHz UWB distributed combiners for multi-antenna receivers

This paper presents discrete active combiners for ultra-wideband (UWB) applications. The proposed solution exploits distributed amplifier techniques to perform the combination of signals over the band 0.5 GHz – 20 GHz. Two circuit boards are demonstrated: a 2-to-1 active combiner with 17 dB gain and a 4-to-1 active combiner with 30 dB of gain. Standard S-parameter measurements have been performed to characterize the presented circuits. Multi-antenna demonstrators have been setup to validate the device functionality in more complex scenarios. In particular combination of wideband and narrowband communications has been demonstrated, as well as the use of the combiners for UWB antenna arrays.

Layout considerations in power amplifiers with negative parallel feedback

In this paper, we discuss layout problems encountered in power amplifiers with negative parallel feedback. We show how to reduce the risk of an unstable power amplifier (PA) by careful layouting without the use of additional elements and thus chip area. Optimised vs. non-optimised layouting are compared and verified with fabricated ICs. Finally a PA with large signal bandwidth of 1.9 GHz at a design frequency of 2.6 GHz using negative feedback in a standard 250 nm BiCMOS technology is introduced. An efficiency of 34% and an output power of 26.9dBm at the 1 dB compression point were measured.

Design and measurements of 50 Ω on-chip slow-wave conductor-backed coplanar transmission lines up to 220 GHz

In this paper high performance slow-wave transmission lines are investigated. The conductor-backed coplanar wave-guides (CBCPW) are manufactured in the back end of line of an high-speed SiGe BiCMOS technology that offers bipolar transistors with ft, fmax of 300 and 500 GHz, respectively. It is therefore important to study the behaviour of transmission lines from below 1 GHz up to 220 GHz. Slow wave structures are compared with conventional CBCPW. The phase velocity of the slow-wave structures is 50 % slower than the conventional CBCPW. Since the wavelength is proportional to the phase velocity, slow-wave structures are more compact than conventional transmission lines. Different de-embedding methods are adopted in order to subtract the pads parasitic to the measurement of the transmission lines. The quality factor of the manufactured slow-wave line is 9.5 despite the small lateral dimension of 64 μm.