Robert Paulo

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier

This paper presents a travelling-wave amplifier (TWA) for wideband applications implemented in a 0.13 μm SiGe BiCMOS technology ( ft= 300 GHz, fmax= 500 GHz). The gain cell employed in the TWA is designed to compensate the synthetic-line losses at high frequencies in order to extend the bandwidth as well as the gain bandwidth product (GBP). A gain of 10 dB and a 3 dB bandwidth of 170 GHz are measured for the fabricated circuit. The circuit analysis is presented to illustrate how the bandwidth of the circuit is dominated by the cutoff frequency of the synthetic lines, thus demonstrating complete losses compensation for the band of interest. The chip required a total area of 0.38 mm 2 and a power consumption of 108 mW. Compared against the state of the art, the presented design achieves the highest reported GBP per power consumption and area, as well as the highest operation frequency for silicon implementations.

250 GHz SiGe-BiCMOS Cascaded Single-Stage Distributed Amplifier

This paper presents a cascaded single-stage distributed amplifier (CSSDA) for wideband applications implemented in a 0.13 μm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). A 3 dB upper frequency of 250 GHz, a bandwidth of 170 GHz, and a gain of 13 dB are demonstrated for the fabricated CSSDA. The circuit requires a chip area of 0.23 mm2 and 74 mW of DC power. Compared against the state of the art, the presented design achieves the highest speed and the smallest area.

High efficient Doherty power amplifier for wireless communication: An RF power amplifier for upcoming radio standards like LTE and LTE-Advanced in microstrip technology

We propose a Doherty power amplifier in microstrip technology which is highly suitable for smaller Long Term Evolution (LTE) and LTE-Advanced base stations such as picocells and femtocells. At the 1 dB compression point it delivers more than 29 dBm output power and exhibits a power added efficiency (PAE) of more than 50% also at the 1 dB compression point. The PAE is still as high as 40% at 6 dB backoff. An intermodulation measurement with this amplifier shows an output intercept point of third intermodulation product (OIP3) of 39 dBm.

Cool silicon ICT energy efficiency enhancements

In this paper, we give an overview of some recent results achieved in the German cluster project Cool Silicon located around Dresden. Cool Silicon features around 50 projects and 100 partners from industry and research institutions, and aims at significantly increasing the efficiency in information and communications technology (ICT). Innovations in micro- and nanoelectronics, circuits, systems, sensors, software and regenerative supply technologies are tackled.

Layout considerations in power amplifiers with negative parallel feedback

In this paper, we discuss layout problems encountered in power amplifiers with negative parallel feedback. We show how to reduce the risk of an unstable power amplifier (PA) by careful layouting without the use of additional elements and thus chip area. Optimised vs. non-optimised layouting are compared and verified with fabricated ICs. Finally a PA with large signal bandwidth of 1.9 GHz at a design frequency of 2.6 GHz using negative feedback in a standard 250 nm BiCMOS technology is introduced. An efficiency of 34% and an output power of 26.9dBm at the 1 dB compression point were measured.

Power-efficient high-frequency integrated circuits and communication systems developed within Cool Silicon cluster project

An overview about research activities in the field of high frequency integrated circuits and communication systems performed within the German cluster project Cool Silicon is given. Cool Silicon is located around Dresden/Silicon Saxony/Germany and features around 50 projects and 100 partners from industry and research institutions, and aims at significantly increasing the energy efficiency of information and communications technologies.

A fully integrated 2.6 GHz cascode class-E PA in 0.25 µm CMOS employing new bias network for stacked transistors

This work presents the design of a differential power amplifier in 0.25µm CMOS with stacked transistors operating in class-E mode. A new analytical approach is derived to design a reactive bias network so that both lower and upper switching transistors retain class-E-like voltage waveforms. By using the bias network simulations show an efficiency enhancement of more than 8 %. In measurements the amplifier achieves an output power of 21.7dBm at an drain efficiency and power added efficiency of 41.5% and 37.9% respectively at a center frequency of 2.6 GHz.

Input transmission line adjustment for efficiency enhancement in Doherty amplifiers

Conventional Doherty power amplifiers need a λ/4 transmission line at the input of the peak amplifier. This provides a 90 degree phase shift of the input signal to allow a phase correct combination at the output. In this paper a discrete Doherty power amplifier for 2GHz LTE band is introduced that comes with a phase shifter at the peak amplifiers input with 110 degree. It shows a 2.5% points higher value for power added efficiency at 1 dB compression point compared to 90 degree phase shift. Furthermore, the degradation of the power added efficiency in the backoff could be enhanced from 27% to 16 %. This amplifier delivers an output power of 31.5 dBm, a gain of 9.5 dB and a power added efficiency (PAE) at the 1 dB compression point of 41% and 34.6% at 6 dB backoff. The maximum efficiency is about 44.3%at 3 dB backoff. It also offers a high linearty with an output referred intercept point of the third order intermodulation (OIP3) of 46 dBm. Common FR4 as substrate and standard electronic components are used. As core element of main and peak amplifier a HEMT FET of the company Avagotech is used. Both amplifiers are equally designed including bias input networks as well as output networks. The only difference of both amplifiers is the operating point whereas main amplifier is working in classAB and peak amplifier in classC mode.

Concept of a stacked feedback PA with on-chip auto-adjusted base voltage of upper transistor

In this paper, we show a power amplifier (PA) with stacked transistors. It is fabricated in a 250nm standard BiC-MOS technology. An adaptive adjustment of the base voltage at the upper transistor ensures equal collector-emitter voltages over the stacked transistors for all operating conditions. Additionally, a slight enhancement of the maximum efficiency was measured. By using an input amplifier with serial negative feedback for gain bandwidth enhancement over the frequency and an output amplifier with parallel negative feedback the PA provides a 3dB gain bandwidth of about 800 MHz and a 1 dB compression point bandwidth of about 1.4 GHz at an operation frequency of 2.6 GHz in measurements.