Christie Delvaux

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Top coat or no top coat for immersion lithography

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the materials refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the materials dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

Comprehensive approach to MuGFET metrology

As we move forward to the 45 and 32nm node, MuGFETs (Multi-Gate Field-Effect Transistor) are considered more and more as a necessary alternative to keep pace with Moores Law. If proven manufacturable, MuGFETs could eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the application of design-based metrology (DBM) to MuGFET OPC validation.

Bottom-ARC optimization methodology for 0.25 μm lithography and beyond

This paper reports on an optimization methodology for BARC/resist processes in order to obtain best CD-control on various substrate topographies. A selection of resist and BARC materials is studied by means of simulations and experiments. Two BARC properties, turned out to be of major importance: planarization effects on topography and etch behavior. The topography itself is very important too: step height and lateral dimensions have a severe influence on CD control. Based on a new evaluation technique, the use of topographical swing curves, the optimum thickness of the BARC layer and of the resist layer are determined.

193nm immersion lithography for high-performance silicon photonic circuits

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.

ArF lithography options for 100-nm technologies

As ArF resists mature, lithographers are pushing the imaging limits as far as possible. ArF lithography is getting ready for the 130nm technology node and currently even the 100nm node printability with ArF is being studied. Since high numerical aperture (NA) ArF scanners are not yet available in volume, strong enhancement techniques will be required to meet these challenging targets at lower NA (0.63NA). In this paper we give an overview of the status of 193nm lithography towards 100nm patterning of memory and logic front-end features, and explore the various enhancement techniques needed. One of the options is off-axis illumination in combination with either a binary or attenuated phase-shift mask. With the use of annular, quadrupole and even dipole illumination, process latitudes of dense and semi-dense features clearly improve as compared to conventional illumination. The main drawback here is the limited depth-of-focus for the isolated lines. A possible solution to this problem is the application of assisting features that makes the diffraction pattern of the isolated lines look more like dense lines. Another proven technique is the alternating phase-shift mask (altPSM) which is known to improve the process latitudes of semi-dense to isolated lines as compared to a binary mask. Design complexity and mask manufacturability are well known problems with altPSM. But issues as image misplacement and the sensitivity to lens aberrations at high coherent light are lesser-known drawbacks for this technique. In this paper we give an indication towards the preferred strategy when 100nm node critical front-end layers of various technologies need to be printed in 193nm. We look at the status of 193nm lithography using the most favourable enhancement techniques, indicating the possible drawbacks. We also indicate where high NA scanners may overcome the restrictions of lower NA lenses.

Front-end-of-line process development using 193-nm lithography

It is expected that 193nm lithography will be introduced in front-end-of-line processing for all critical layers at the 100nm node, and possibly also for some layers at the 130nm node, where critical layers are required to have the lowest mask cost. These processes are currently being investigated at IMEC for CMOS logic applications. While the lithographic performance of 193 nm resists has improved significantly in the last year, most materials still have important processing issues that need further improvement. On one hand, the resists material itself suffers from for example poor dry etch resistance and SEM CD shrinkage. On the other hand, interaction with other materials such as SiON inorganic ARCs becomes more challenging in terms of footing behavior, adhesion, and line edge roughness. In this paper, the 193nm processing experience gained at IMEC will be outlined, as well as solutions for manufacturability. Front- end-of-line integration results will also be shown, mainly for gate applications. It will be demonstrated that currently several commercial resist are capable of printing 130nm gates within the +/- 10 percent CD tolerance, even after gate etch. The impact of line edge roughness will also be discussed. Finally, the feasibility of printing 100nm logic patterns using only binary masks has been demonstrated, including gate etch.

Status of ArF lithography for the 130-nm technology node

Lithographers are preparing their processes for the 130nm node. About one year ago, first generation full field ArF step and scan systems have been introduced in a number of fabs. These systems have lenses with numerical apertures in the order of 0.6. At the same time, 0.7 NA KrF step and scan systems have been introduced as well. Also last year, KrF resists were shown to be much more mature than ArF resists.

Precuring implant photoresists for shrink and patterning control

Polymeric photoresists are readily being used as the stopping layer for ions during implantation processes in manufacturing of integrated circuitry. In order to be compatible for standard optical lithography with deep ultraviolet exposures, the state-of-the-art resists are chemically amplified; as they are for photoresists for etch patterning. Partially deprotected, including patterned, photoresists contain a range of small molecular weight species that are prone to escape the resist if the resist was to be irradiated by additional UV-light, electron beams or ion bombardment. For implant processes in device integration this is becoming progressively the most topical issue for aggressive nodes, where 193 nm compatible resists are progressively turning out to be the new platform for implant lithography. These will shrink significantly during the ion implantation and subsequently produce undesired doping gradients on a length scale comparable to the target feature width. In addition, conventional UV-flood exposure that is common for 248 nm resist platforms is not directly transferrable to 193 nm resists. In this paper, we explore the precuring options available for state-of-the-art implant photoresists for 193 nm lithography, in which we target to reduce the shrinkage during implantation for trench critical dimensions that are relevant for nodes below 20 nm. We present an extensive study comprising of different approaches, including laser-, ion- and electronbased treatments. Each treatment is individually investigated with the aim not only to find a valid pretreatment for shrinkage control during implantation, but also to fundamentally understand what effect alternative pretreatments have on the profile and dimensions of thick photoresists used as implant stopping layers. We find that there are viable options for further process optimization in order to integrate them into device process flows. To this extent, we show the shrink behavior after pretreatment and compare the additional shrink dynamics after implantation.