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Kinetic investigation of copper film oxidation by spectroscopic ellipsometry and reflectometry

This article presents the oxidation kinetics of Cu thin films in dry and wet oxygen at temperatures from 100 to 600 °C. Spectroscopic ellipsometry and reflectometry, which yield refractive index and thickness of the Cu oxide, were used in kinetic study of Cu film oxidation. Cabrera–Mott (C–M) theory was used for the calculation of oxidation activation energies, yielding 0.68 eV for dry oxidation and 0.43 eV for wet oxidation. The scanning electron microscopy (SEM) and Rutherford backscattering spectrometry were used to investigate the cross-sectional profile, grain size, and chemical composition of the Cu oxides. A formula for Cu oxide thickness calculation was derived from the C–M theory and experimental data. Good agreement has been observed in thickness values from formula calculation, spectroscopic reflectance and SEM has been confirmed. A study of the effect of trace O2 on Cu film anneal is also presented.

In Situ Rapid Thermal Oxidation and Reduction of Copper Thin Films and Their Applications in Ultralarge Scale Integration

Copper is widely accepted as a next-generation metallization material for ultralarge-scale integration (ULSI) because of its low resistivity and high electromigration resistance, It is well known that Cu oxidizes easily at low temperatures. This characteristic has impeded the application of Cu in integrated circuits. However, the high oxidation rate of Cu and high reduction rate of its oxides at low temperature can be exploited for some potential applications This paper presents the kinetic studies of Cu film oxidation and in situ reduction of its oxide films, The Cu oxidation experiments were performed in dry and wet oxygen at temperatures from 100 to 600°C for oxidation times from 10 to 718 S. Scanning electron microscopy. Rutherford backscattering spectrometry, spectroscopic ellipsometry and reflectometry, and X-ray photoelectron spectroscopy were used for analyzing the chemical composition of the processed material and determining the oxidation/reduction kinetics of the films. The results showed that the oxide phase is CuO at higher temperature and Cu 2 O at lower temperature (<400°C). In situ reduction of copper oxide was studied using secondary ion mass spectroscopy, indicating that the reduction of Cu oxides proceeds from the interface to the surface with a high reduction rate. The infrared reflectivity of Cu surface is over 99%. This is a problem when the Cu process is performed in a rapid thermal processing (RTP) system since most of the radiation from the lamps is consequently reflected by the Cu surface. An improved process called shield-enhanced RTP, results in higher lamp power efficiency and better within wafer temperature uniformity.

RTP application and technology options for the sub-45 nm nodes

As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovations and changes in CMOS device architecture, RTP will play a major role in the story. RTP will contribute in gate-stack engineering, oxidation processes, ultra-shallow junctions, silicide formation, low-k dielectric annealing and in fundamental improvement of thin film properties. As device dimensions are controlled at the atomic scale, the concepts of thermal budget reduction will continue to drive the technology, with reductions in both process times and process temperatures combined with control of a very high purity process gas ambient. The thermal and ambient flexibility of RTP will become even more important as processes are developed and optimized for new gate dielectrics, high-mobility channel designs and metal gates combined with device architecture changes such as multiple-gate transistor designs. As the transistor channel length scales towards the ultimate limit imposed by atomic-scale fluctuations and quantum effects, the need for minimization of parasitic resistance and capacitance will become increasingly dominant in device performance. Here, the most critical requirements are to increase the concentrations of electrically active dopants without inducing excessive diffusion and to reduce contact resistances. These challenges will be met through innovation in RTP that addresses opportunities in materials engineering and in thermal cycle design. Further advances in silicon device technology will ultimately be limited by manufacturing costs. Pressure for manufacturing cycle-time reductions will mean that single-wafer processing technologies, including RTP, will continue to displace batch processing approaches. The final blow for the batch furnace will come from the transition to even larger wafer sizes, where the planar heating geometry inherent in RTP provides a natural fit to the wafer

The future of RTP, a technology that can change the IC fab industry

RTP presents a unique opportunity for the semiconductor industry. By completing the transition to RTP as we enter the 300 mm-era, the industry can seize the opportunity for significant improvements in cycle-time, in thermal budget minimization and in process performance. This paper examines how RTP has evolved to meet these challenges and describes the state-of-the-art of RTP technology today. The poor throughput performance of 300 mm batch furnaces, the risk of misprocessing large batches of very valuable wafers and the inflexibility of the furnace in an era when cycle-time is paramount all signal the end of large-batch thermal processing within this decade.

Growth and Characterization of Rapid Thermal Chlorinated Oxides Grown Using In Situ Generated HCl

We present here a rapid thermal processing (RTP) technique that uses in situ generated HCl for growing chlorinated oxides. A gas mixture consisting of oxygen and a benign organic precursor was made to flow over the heated wafer surface where the gases reacted to generate the HCI at the wafer site. This method is a considerable improvement over all of the existing chlorination techniques because it provides much higher safety, lower contamination potential, greater process simplicity, and is produced at a lower cost. Our data on thin oxides shows that in situ chlorination provides benefits that are similar to those of conventional chlorination methods, namely, oxides with lower interface states and higher growth rates than those of standard dry oxides. Secondary ion mass spectrometry plots show that no carbon is introduced in the chlorinated oxide even though it is grown directly in the presence of an organic precursor. Other electrical data demonstrates no degradation in leakage current and charge trapping through chlorination.

Rapid thermal curing of low-k spin-on films

We have used short time, high temperature, and high ramp-rate thermal cycles for curing organic low-k spin-on films in a rapid thermal processing (RTP) system. We show that such cycles can give lower copper diffusion through barrier layers than the conventional low temperature, long duration cycles carried out in furnaces. In addition, a highly controlled ambient is needed to prevent film oxidation. All of these requirements make RTP ideally suited for low-k film curing. Therefore, RTP can enable integration of low-k films in advanced interconnect schemes.

Applications of rapid thermal process to nitridation of tungsten and denudation of WN/sub x/ for poly-Si/Metal gates

To reduce gate RC delay in sub-100 nm CMOS devices, a poly-Si/metal gate electrode stack, consisting of W/barrier/poly-Si layers has become an attractive candidate. Recent studies show that rapid thermal annealing (RTA) of amorphous WN/sub x//poly-Si resulted in denudation of nitrogen atoms with simultaneous in situ formation of low resistivity W and highly reliable barrier layer. This process indicated some advantages, i.e. there is no need for barrier interface, yet device properties superior to those of conventional W/WN/sub x//poly-Si gate has been achieved. The purpose of this paper is to report a study of tungsten nitridation and WN/sub x/ denudation using RTP in various gas ambients, including N/sub 2/, Ar, forming gas (10% H/sub 2/ in Ar), wet H/sub 2/ (16% H/sub 2/O in H/sub 2/) and NH/sub 3/. RTA in a spike fashion in NH/sub 3/ or wet H/sub 2/ for only 2 seconds was used to convert 50 nm WN/sub x/ to pure W. Auger electron spectroscopy (AES) studies indicated that the in situ interface barrier formation with high nitrogen content was completed during the denudation of WN/sub x/.