Peter Debacker

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moores Law. For the first time, the performance of two GAA device options- lateral FET (LFET) and vertical FET (VFET)-is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi-Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.

Standard cell design in N7: EUV vs. immersion

While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Abstract. Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.

An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard

Multi-gigabit LDPC decoders are demanded by standards such as IEEE 802.11ad and IEEE 802.15.3c. In order to achieve high throughput, most published multi-gigabit designs use row-paralleled architecture. In this paper, we proposed a half-row paralleled LDPC decoder with half layer level pipeline and single permutation network for the 802.11ad standard, which reduces the hardware resources almost by half compared to the state-of-the-art row-paralleled LDPC decoder, achieving a good trade-off between energy efficiency and area efficiency. The decoder achieves a throughput of 5.6 Gbps and consumes only 99 mW for the highest coding rate 13/16 at 5 iterations, working at 500 MHz by using 40nm G technology, yielding an energy efficiency of 3.53 pJ/bit/iteration and area efficiency of 35 Gbps/sqmm.

Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

Aggressive power supply voltage Vdd scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vdd results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal Vdd condition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.

A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of the transformation towards 4G. In this paper, we describe an energy efficient multi-Gbps LDPC decoder engine based on ASIP using Target tool suite. The ASIP core can be configured as half-layer paralleled or quarter-layer paralleled decoding, which offers a good trade-off between the throughput and power/area efficiency when compared to the state-of-art fully paralleled ASIC based multi-Gbps LDPC decoder. When the ASIP core is instantiated for 802.11ad, it achieved a throughput up to 5.3 Gbps at 5 iterations with a latency of less than 150 ns and a record energy efficiency of 4.3 pJ/bit/iteration in 40G TSMC technology for the coding rate 13/16, showing to be competitive versus published ASIC solutions.

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with the efficiency of the Compact Digital Waveform (CDW) representation. That way, we capture the true workload-dependent BTI-induced degradation of selected CPU components. First, we show that existing works that assume constant stress patterns fail to account for workload dependency leading to fundamental estimation errors. Second, we evaluate the impact of different real workloads on selected CPU sub-blocks from a commercial processor design. To the best of our knowledge, this is the first work that combines atomistic property and true workload-dependency for variability analysis.

Computation-skip error resilient scheme for recursive CORDIC

Aggressive voltage and frequency scaling are widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical voltage or frequency results to numerous timing errors, and hence unacceptable output quality. In this paper, a computation-skip (CS) scheme is proposed for recursive digital signal processors with a fixed cycles per instruction (CPI) to correct timing errors. A CORDIC processor with the proposed CS scheme still functions when scaling beyond the sub-critical voltage or frequency. It improves EVM by 47.9 dB at its most critical frequency or supply voltage, and extends the voltage scaling limit by 90 mV w.r.t the conventional CORDIC. Besides, it is more than 1.7X energy efficient w.r.t. the conventional high-speed CORDIC, which is designed for a more aggressive scaling.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

A novel positioning technique for 2.4GHz ISM band

Accurate indoor positioning is very challenging. At this time, no solutions exist that can offer accurate distance measurements over large ranges. In this paper, we present a novel ranging technique. It offers sub-meter accuracy in indoor environments and can maintain this accuracy over hundreds of meters. Currently, this ranging technique has been demonstrated with a dedicated PCB implementation that confirms the unique combination of accuracy and range.