Peter G. Tolchinsky

Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory

Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-µA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.