Peyman Pouyan

Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime

Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.

Reliability challenges in design of memristive memories

The demand for highly scalable and low power memory has led to research in emerging technologies and devices. Among these devices, memristors has attracted increased attention as being a promising storage device. However, due to its nano-scale size it faces various types of reliability issues. In this study, we have reviewed the memristive mechanisms and reliability concerns existing in memristor memory design. Then, we have simulated the ionic drift memristor model in presence of the process variability. Next, by considering a normal distribution for the resistive distribution of memristors in LRS and HRS state we have shown the instabilities and probability of failure in read and write procedure of memristive memories, and highlighted the requisite and motivation for the reliability aware memristive circuit design.

Statistical lifetime analysis of memristive crossbar matrix

Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.

New reliability mechanisms in memory design for sub-22nm technologies

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to users requirements.

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbar-based memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65 percent in comparison with non-adaptive reconfiguration strategy.

RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics (such as high scalability, CMOS compatibility and non-volatility) to replace the current conventional memories. However, process variation due to nano-scale structure poses major challenges on both reliability and yield. This has led to the investigation of new robust design strategies at the circuit and system level. This paper first reviews the RRAM variability phenomenon and the state-of-the art variation tolerant techniques at the circuit level. Thereafter, it analyzes the impact of variability on memory reliability, and proposes a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.

Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design

Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X.

An experience with chalcogenide memristors, and implications on memory and computer applications

Memristors are considered a promising emerging device that may improve some specific applications, like memories, or make feasible new ones, mainly alternative computing architectures. However, it is not a mature technology and their characteristics can vary significantly depending on their structures. Also, variability and reliability might suppose an important issue in some applications. In this paper, a chalcogenide memristor is studied and their main parameters are extracted. Then, its discused how their properties can affect two applications: a memory circuit and a digital computing alternative, the logic implication technique.

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.