Philip L. Hower

A Rugged LDMOS for LBC5 Technology

This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.

Safe operating area - a new frontier in Ldmos design

The boundaries that determine the Ldmos safe operating area are described and are shown to be predominantly thermal or electrical in origin. Methods of characterizing and analyzing the related thermal SOA and electrical SOA are illustrated. The impact on device size and related trade-offs with breakdown voltage and specific on-resistance are discussed, as are possibilities for improving SOA performance.

Short and long-term safe operating area considerations in LDMOS transistors

Lateral DMOS transistors are widely used in mixed-signal IC circuit designs, particularly where power handling is important. This paper views the LDMOS from a power-handling perspective, considering both design and characterization aspects. The complex nature of the LDMOS safe operating area (SOA) can be dealt with by considering long-term and short-term operating conditions. Long-term conditions are covered by a hot carrier SOA, and short-term conditions are further sub-divided into electrical SOA and thermal SOA. Characterization examples of the various kinds of SOA are given.

Avalanche-induced thermal instability in Ldmos transistors

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

Current status and future trends in silicon power devices

Overall, power semiconductors are very much alive and well. Silicon dominates the field with a high quality R&D effort and manufacturing workforce supported by an extensive infrastructure. Much of this success can be linked to the numerous desirable material properties of silicon. These include the presence of a native oxide with low interface state density, reasonable values for hole and electron mobilities, a high critical electric field, high carrier lifetimes, and finally, good thermal conductivity. Other materials, for example SiC and GaN, are superior to silicon in some of these properties. This has led to product applications where a particular need dominates the application. For example, SiC has a higher critical field vs. silicon. This permits the design of 600V SiC Schottky diodes that are superior to their silicon counter parts, whether it is a p-n junction or a Schottky diode. Because such developments enhance the overall industry, we should encourage them. Nevertheless, it seems that power semiconductors will continue to be dominated by silicon for the next few decades.

ESD robust bipolar transistors with variable trigger and sustaining voltages

A new pseudo-vertical integrated npn bipolar transistor with variable sustaining and trigger voltages is presented in this paper. It is shown that the sustaining voltage can be tuned to obtain the required high value. These devices are realized in a junction isolated (JI) mixed-signal power BiCMOS technology with maximum breakdown voltage requirements in excess of 60V. The ESD robustness of these bipolar transistors is verified using transmission line pulse (TLP) and HBM (human body model) measurements. It is now possible to use a single bipolar transistor as an ESD protection device for a high voltage pin application instead of using stacked bipolar devices. The net result is a better control and possible reduction in overall die area.

Anomalous temperature behavior in LDMOS current sensing

A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge in the power LDMOS that arises from a seemingly unrelated change in the hydrogen anneal temperature in the back end. The physical mechanism leading to the anomaly and the interaction between temperature mismatch and metal layout are presented.