Philippe Cathelin

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.

The Experimental Demonstration of a SASP-Based Full Software Radio Receiver

Many technological bottlenecks prevent from realizing a software radio (SR) mobile terminal. The old way of building radio architectures is now over because a single handled terminal has to address various communication standards. This paper exposes a SR receiver: a sampled analog signal processor (SASP) is designed to perform downconversion and channel presorting. The idea is to process analog voltage samples in order to recover in baseband any RF signal emitted from 0 to 5 GHz. An analog fast Fourier transform achieves both frequency shifting and filtering. An experimental demonstrator of the SASP using 65 nm CMOS technology from STMicroelectronics is here presented and measured. It validates the concept of a new SR receiver with the design of a demonstrator which runs at 1.2 GHz consuming 389 mW.

The first experimental demonstration of a SASP-based full Software Radio receiver

This paper presents the principles of a Sampled Analog Signal Processor (SASP) dedicated to Software Radio mobile device. Many technological bottlenecks are to be overcome. The idea is to design a discrete analog signal processor to challenge theses bottlenecks. The main issue associated with the A/D conversion is thus avoided. The SASP aims to select a spectral envelope of a RF signal among all RF signals. To reach that target, the SASP processed analogically the RF input signal spectrum thanks to an analog Discrete Fourier Transform (DFT). Once the spectrum processed, only the voltage samples representing the signal envelope to be treated are converted into digital. The selection of few voltage samples among thousands others replaces the classical mixing and filtering operations. It dramatically reduces the A/D conversion frequency from GHz to MHz frequencies. Design strategy, applications and for the very first time, measurements are presented.

65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

The software-defined radio (SDR) concept aims at designing a re-configurable radio architecture accepting all cellular or non-cellular standards working in the 0-5 GHz frequency range. Some technical challenges have to be solved in order to address this concept. A fully digital SDR system implying an A/D conversion close to the antenna is not feasible in the case of mobile terminal. This paper presents the design of an analog processor which process RF signal in order to elect and convert into digital only the desired RF signal envelope. It uses the principle of a fast Fourier transform (FFT) to carry out basic analog functions with high accuracy at a low power consumption. Schematic and post layout simulations are exhibited. Estimated die area and power consumption are numbered.

From Software-Defined to Software Radio: Analog Signal Processor features

The RF transceivers architectures are to integrate the concept of Sotware Radio. But, in the case of mobile terminal, hard constraints are imposed by the factor of mobility. Low power and very complex circuits are claimed by the telecommunication industry. Classical architectures are no more sufficient to challenge this goal. New systems are thus proposed, and the concept of Software Defined Radio (SDR) is a step on the roadmap toward Software Radio (SR). This paper presents a state of the art of SDR circuits and explores the application of a Analog Signal Processor SR chip.

27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI

A variety of emerging applications in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no longer viable. To address this issue, recent work has proven the viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts the burden to a CMOS substrate, which must provide dense signal conditioning and processing before the massively parallel image data can be pushed off chip. A common approach for data reduction is to employ subarray beamforming (BF), which applies delay and sum operations within a group of pixels. To implement such functionality within the tight pixel pitch, prior works have implemented the delays using simple S/H circuits [2] or analog filters [3], and typically suffer from a combination of issues related to limited delay, coarse delay resolution and limited SNR.

A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers

This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NF and better than 75 dB inter-receiver isolation.