Phung T. Nguyen

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

High performance and low power transistors integrated in 65nm bulk CMOS technology

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Scalability and biasing strategy for CMOS with active well bias

We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.

Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.

Dual work function metal gate CMOS using CVD metal electrodes

Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO/sub 2/. T/sub inv/ as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole mobility has been obtained for aggressive stacks. It is further observed that electron mobility optimization is critically dependent on specific electrode and interface layer combinations along with post deposition processing even for nominally identical HfO/sub 2/ layers.

Nonrandom Device Mismatch Considerations in Nanoscale SRAM

Competitive density, performance, and functional objectives of the SRAM bit cell require design rules which are much more aggressive than those used in base logic designs. Because soft fail yield in SRAM is dependent on the device threshold and threshold mismatch in the bit cell, much research has been directed toward addressing the random contributors to within-cell device threshold variation. We examine four sources of potential nonrandom threshold mismatch that can arise from the use of aggressive design rules in the bit cell: 1) implanted ion straggle in SiO2; 2) polysilicon inter-diffusion driven counter-doping; 3) lateral ion straggle from the photoresist; and 4) photoresist implant shadowing. Using simulation and hardware measurements, we quantify the device parametric impacts and provide a statistical treatment forming the basis for quantification of the functional margin impacts on the bit cell. We examine two lithography-compliant bit-cell layout topologies and quantify the impact of systematic mismatch on the margin limited yield.