Ping-Chuan Wang

The effect of a threshold failure time and bimodal behavior on the electromigration lifetime of copper interconnects

Electromigration results are described for a Dual Damascene structure with copper metallization and a low-k dielectric material. The failure times follow a bimodal lognormal behavior with early and late failures. Moreover, there is evidence of a threshold failure time such that each failure mode is represented by a 3-parameter lognormal distribution. It is found that the threshold failure time scales differently with current density from the median time to failure, which can be explained by considering two components of the electromigration lifetime: one controlled by void nucleation and the other controlled by void growth.

Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress

A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f/sub T/ and 100 GHz f/sub max/. Accelerated current stress up to as high as J/sub C/=34 mA//spl mu/m/sup 2/ was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interfacial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10/sup 6/ hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

CVD Co capping layers for Cu/low-k interconnects: Cu EM enhancement vs. Co thickness

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6nm.

Implications of a threshold failure time and void nucleation on electromigration of copper interconnects

Electromigration results are described for a dual damascene structure with copper metallization and a low-k dielectric material. The failure times follow a 3-parameter lognormal behavior, with a threshold failure time needed to represent the entire failure distribution. We found that the threshold failure time scales differently with current density from the median time to failure, which has significant implications for making reliability predictions. It is shown that the threshold failure time corresponds to damage (presumably voids) nucleation of the electromigration process. The observed current density dependency, along with scanning electron microscopy cross sections of stressed samples and Monte Carlo simulations of failure distributions, suggests that both void nucleation and void growth should be considered for accurate modeling of the electromigration lifetime.

Electromigration threshold in single-damascene copper interconnects with SiO/sub 2/ dielectrics

We demonstrate the electromigration threshold, or the so-called short-length effect, in single-damascene copper interconnects with SiO/sub 2/ dielectrics. With standard electrical lifetime measurements and a simplified equation based on the Blech model, the length-dependent electromigration behavior is studied quantitatively over a temperature range between 295/spl deg/C and 400/spl deg/C. It is shown that the electromigration threshold becomes more prominent with decreasing temperature. The applicability of the proposed equation is justified, and the practical aspects of the electromigration threshold in copper technologies are discussed.

Correlation between a threshold failure time and void nucleation for describing the bimodal electromigration behavior of copper interconnects

Electromigration testing of an interconnect system comprised of copper metallization and a low-k dielectric material gives rise to bimodal lognormal statistics with early and late fails. When separated from one another, we observed failure modes characterized by a three-parameter lognormal distribution and the same threshold failure time. It is shown that the threshold failure time corresponds to damage (presumably voids) nucleation of the electromigration process. The dependence of the threshold failure time and the median time to failure on current density suggests that both void nucleation and void growth need to be considered for accurate modeling of the electromigration lifetime.

Integration and reliability of CVD Ru cap for Cu/Low-k development

Selective CVD Ru cap deposition process has been developed for BEOL Cu/Low-k integration. Selectivity of CVD Ru deposition between Cu and dielectrics is investigated. Electrical performance, electromigration (EM) lifetime, voltage ramp (I–V), and time -dependent-dielectric-breakdown (TDDB) are also characterized for Cu interconnects capped with CVD Ru. This selective CVD Ru cap process is a good candidate for 22nm and beyond technology nodes.

Electromigration Results with Large Sample Size for Dual Damascene Structures in a Copper/CVD Low-k Dielectric Technology

The reliability of a two-level electromigration structure stressed under various conditions is described. The structure consists of Cu dual damascene metallization with SiCOH as the low-k dielectric. A new electromigration test system is implemented to greatly increase the sample size without significantly increasing the hardware requirements. Due to the presence of two failure modes, the statistical behavior is described by a bimodal lognormal failure distribution. Failure analysis indicates that early failures occur in the Cu vias while late failures occur in the Cu lines. Comparable current density exponent and activation energy values are obtained for both failure modes, suggesting similar void formation mechanisms

Interconnects exhibiting enhanced electromigration short-length effects by line width variation

A novel model and approach for obtaining improved electromigration short-length effects are reported. The results for a structure with Dual Damascene copper-based metallization and two width regions demonstrate that increasing the line width for a portion of the line length generates longer electromigration lifetimes. Moreover, the lifetimes are accurately characterized by introducing an equivalent length for the structure that depends on the width and length of each region. The results are explained in terms of a modulation of the stress profile in the structure with more than one width region. A consequence of these findings is increased design flexibility since more options are available to improve the electromigration reliability of short interconnects.

Electromigration extrusion kinetics of Cu interconnects

Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation energy for extrusion fails was determined to be 1.13 eV, comparable to the value of 0.99 eV for the resistance shift fails. This suggests the same failure mechanism for two failure modes: Cu mass transport primarily along the Cu/cap interface. The current exponent was extracted as 1.48 and 1.36 for extrusion fails and resistance shift fails, respectively. Physical failure analysis confirmed Cu extrusion near the anode and void formation at the cathode. Samples with improved pre-clean process before the cap deposition significantly suppressed EM induced extrusions, indicating a mechanically stronger Cu/cap interface. Furthermore, effective atomic sink at the anode end appeared to reduce the compressive stress buildup during EM, as it also significantly mitigated EM induced extrusion.