Paul S. McLaughlin

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

Line edge roughness and spacing effect on low-k TDDB characteristics

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.

The Effect of Metal Area and Line Spacing on TDDB Characteristics of 45nm Low-k SiCOH Dielectrics

Low-k time-dependent dielectric breakdown (TDDB) is rapidly becoming one of the most important reliability issues in Cu/low-k technology development and qualification. Although considerable progress has been made in recent years in addressing the electric field dependence of low-k time-to-breakdown (tBD), there has been very little comprehensive work done on the effect of metal area and line spacing on low-k TDDB. The lifetime of a product chip is typically obtained by extrapolating TDDB data from small test structures to large chip areas, and the low-k TDDB line spacing scaling rule normally should be considered for the definition of operating voltages for various technologies to assure long-term reliability. Therefore, both area scaling and line spacing scaling relations are of great importance, in order to have a robust technology qualification. In this study, a thorough investigation into the 45 nm low-k SiCOH TDDB was conducted in order to understand the breakdown failure statistics, to model the area dependence, and to explore the line spacing scaling. With the help of experimental results and computational simulations, the effect of line-to-line spacing on low-k TDDB was clearly identified and a methodology for accurate determination of Weibull shape factor is proposed.

Impact of via-line contact on Cu interconnect electromigration performance

Damascene processing creates special features for copper interconnect electromigration (EM). Though the fast Cu diffusion path is along the interface between Cu and the top cap layer, the early EM fails are often associated with vias, either by voiding in the via (via depletion), or by voiding underneath the via (line depletion). While most of the early EM fails for via depletion are related to the liner quality in vias, for line depletion EM the contact configuration between the via and the underlying line is critical to the failure characteristics. The contact between the via and the line liner below can effectively prevent or minimize open-circuit type EM failures. Redundant vias can significantly improve the EM performance in both the median failure time (t/sub 50/) and the distribution shape (sigma, /spl sigma/), depending on the arrangement of these vias relative to the line below. This paper presents an EM study of Cu interconnects with various via/line contact configurations. Results from single via and multiple via contacts, with and without redundancy to the underlying lines, are discussed.

The effect of a threshold failure time and bimodal behavior on the electromigration lifetime of copper interconnects

Electromigration results are described for a Dual Damascene structure with copper metallization and a low-k dielectric material. The failure times follow a bimodal lognormal behavior with early and late failures. Moreover, there is evidence of a threshold failure time such that each failure mode is represented by a 3-parameter lognormal distribution. It is found that the threshold failure time scales differently with current density from the median time to failure, which can be explained by considering two components of the electromigration lifetime: one controlled by void nucleation and the other controlled by void growth.

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric

The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence, on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur as well as a correlation between the test structure yield and reliability are also reported.

Statistical Evaluation of Electromigration Reliability at Chip Level

Chip level electromigration (EM) reliability is determined by: 1) the element level EM failure probability used for design guideline generation; and 2) the distribution of EM elements against design limits. Balancing these two factors is critical for a chip design to achieve the best performance while maintaining chip level EM reliability. This paper discusses the relationship between element level and chip level EM failure probability and provides examples of EM evaluation of chip designs.

Electromigration Challenges for Nanoscale Cu Wiring

Electromigration data and a theoretical model have shown that Cu lifetime in on‐chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density. In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo‐like structure observed for <90 nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion. The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated. The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes. The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffus...

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.