Vempati Srinivasa Rao

Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect

In advanced electronic products, current crowding induced electromigration failure is one of the serious problems in fine pitch flip chip solder joints. To explore a strong resistance against current crowding induced electromigration failure, a very thick Cu column bump combined with a shallow solder interconnect at 100μm pitch for flip chip applications has been studied in this paper. Results revealed that these interconnects do not fail after 720h of current stressing at 100°C with a current density of 1×104A∕cm2 based on the area of interface between Cu column bump and solder. The reduction of current crowding in the solder region by using thick Cu column bumps increased the reliability against electromigration induced failure. The current distribution in a flip chip joint of a Cu column bump combined with a shallow solder has been confirmed by simulation. However, Kirkendall void formation was found to be much serious and enhanced by electromigration at the Cu∕Cu3Sn interface due to the large Cu∕Sn ra...

Development of 3D silicon module with TSV for system in packaging

Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.

Development of 3-D Silicon Module With TSV for System in Packaging

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

TSV interposer fabrication for 3D IC packaging

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

A thick photoresist process for advanced wafer level packaging applications using JSR THB-151N negative tone UV photoresist

The development of thick photoresist molds using JSR THB-151N negative tone UV photoresist for the electroplating of interconnects in advanced packaging technologies has been demonstrated. Two different thick photoresist molds 65 and 130 µm high with aspect ratios of up to 2.6 have been fabricated with good reproducibility using single and double coating processes. Optimized lithography parameters using a UV aligner to achieve straight and near-vertical side-wall profiles are also reported. Near-vertical side walls similar to that obtained using SU-8 photoresist have been obtained. JSR photoresist has been found to be easily striped with no residues in solvent stripper solutions, making it suitable for wafer bumping applications and the processing of MEMS devices. Through-mold electroplating of copper and solder is also demonstrated. The simultaneous fabrication of 1167 000 high density interconnects on 8 inch wafers, using lithography and electroplating technologies, is also reported.

Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure

Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures from 100 to 140 °C, the increasing of electrical resistance under current stressing was mainly due to the formation of the high temperature intermetallic compounds (IMCs). The resistance increase-rate in solder bump interconnects was faster than that of Cu post with SnAg bump joints since there was more low temperature solder and under current stressing, more IMCs would be formed. When Cu post with SnAg bumps were tested at 140 °C with the current density of 4.08×104 A/cm2, after certain stressing time the resistances would reach a plateau region, where the diffusion between different materials, i. e., Cu, Ni and Sn reached equilibrium, and IMCs became stable. Large number of Kirkendall voids and a number of cracks were found in the Cu post interconnects which was caused by the electron wind since less voids and cracks were found in the adjacent bump interconnects. When Cu post with SnAg bumps were tested at 140 °C with the current density of 2.04×104 A/cm2 for 1000 h, the resistance did not reach steady state. The electron flow direction also has an effect on the diffusion of materials. The degradation of resistance increased faster when electrons flow from Cu UBM to ENIG.

Development of coaxial shield via in silicon carrier for high frequency application

System-in-package (SiP) based on silicon carriers is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through wafer interconnects. The development of SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to substrate crosstalk and poor RF performance. In this paper, a novel coaxial shielded via in silicon carrier is presented for high frequency applications. Electrical modeling was carried out to obtain the required geometries for optimum performance. The coaxial shield via is able to suppress undesirable substrate crosstalk between vertical interconnects as well as provide excellent RF performance. The detailed fabrication process is also presented. A negative tone SU-8 photoresist is used as the dielectric for the coaxial shield via structure. A test vehicle is fabricated on 8-inch, 10 Omegamiddotcm resistivity silicon wafer with a target of achieving a transmission coefficient, S21 of greater than -0.5 dB at 40 GHz. SU-8 dielectric of approximately 112 mum thickness was deposited on the via sidewall of a 300 mum diameter through wafer via holes, and the via-holes filled with copper using bottom up electroplating approach to achieve a radius ratio, n of 4

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.

FCBGA Package With Through Silicon via (TSV) Interposer

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.