Veeraraghavan S. Basker

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High-

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,<i>L</i>_GATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of <i>R</i>_ON - <i>L</i>_GATE (dR_ON/dL_GATE), transconductance <i>G</i>_MSAT, and injection velocity (<i>v</i>_inj) measurements indicate a ~ 15% mobility-induced <i>I</i>_ON enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.

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The natural choice to achieve multiple threshold voltages (Vth) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth. This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple Vth solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. We also show that Vth extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.

/Metal-Gate nFinFETs for High-Performance Logic Applications

We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.

Channel doping impact on FinFETs for 22nm and beyond

A significant increase in parasitic resistance (R<inf>PARA</inf>) fluctuation is observed when S/D length is getting smaller than the characteristic length (L<inf>TRANS</inf>). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the analytical model. Further R<inf>PARA</inf> fluctuation improvement can be realized by optimizing the L<inf>TRANS</inf>.

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

Hot-carrier degradation (HCI) in aggressively scaled undoped-body devices is carefully studied and compared for high-k/metal gate FINFETs and extremely thin silicon-on-insulator (ETSOI) transistors. We show that HCI involves different degradation mechanisms for silicon-on-insulator (SOI)-FINFETs and ETSOI devices though both are fabricated on undoped body. For FINFETs, the HC degradation correlated with interface trap generation in the channel region, whereas for ETSOI, trap generation and electron trapping in the spacer-nitride region were observed.

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

A methodology based on the transistor body effect is used to monitor inversion oxide thicknesses (Tinvs) in high-κ/metal-gate undoped ultrathin-body short-channel SOI FINFETs. The extracted Tinvs are benchmarked to independent capacitance-voltage (C-V) measurements. For the first time, device simulation is introduced to understand the fundamental difference in Tinv values extracted using the two techniques, which is driven by the inversion charge centroid at different bias conditions.

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS

Multi-channel gate all around (GAA) semiconductor devices require measurements of more target parameters than FinFET devices, due in part to the increased complexity of the different structures needed to fabricate nanosheet devices. In some cases, multiple measurement techniques are required to be used in a hybrid-metrology technique in order to properly extract the necessary information. Optical scatterometry (optical critical dimension, or OCD) is an inline metrology technique which is used to measure the geometrical profile of the structure, but it may not ordinarily be sensitive to very small residues. X-ray based metrologies, such as x-ray fluorescence (XRF) can be used to identify which materials are present in the structure, but are not able to measure profile information for complex 3D structures. This paper reviews a critical etch process step, where neither OCD nor XRF can extract all of the necessary information about the structure on their own, but, when hybridized, are able to provide enough information to solve the application. In GAA structures, the nanosheets are formed from alternating layers of thin SiGe and Si layers which are deposited on a bulk Si substrate. To form the nFET channel, the SiGe must be removed. However, in some cases, there is still remaining SiGe residue on the surface of the Si nanosheets, present in small amounts that are difficult to measure with conventional OCD. Additionally, it is desirable to know at which level of the stacked nanosheets the residue is present. In order to properly characterize the amount of SiGe remaining, data from both OCD and XRF are used. By measuring before and after the etch, the XRF can calculate the percentage of SiGe that is remaining after the etch. This percentage can be used as a constraint in the OCD model to allow the OCD to accurately measure the amount of SiGe, and to enable the OCD model to identify the location of the residue.