Purnendu K. Mozumder

Statistical feedback control of a plasma etch process

This paper presents the methodology developed for the automatic feedback control of a silicon nitride plasma etch process. The methodology provides an augmented level of control for semiconductor manufacturing processes, to the level that the operator inputs the required process quality characteristics (e.g. etch rate and uniformity values) instead of the desired process conditions (e.g., specific RF power, pressure, gas flows). The optimal equipment settings are determined from previously generated process/equipment models. The control algorithm is driven by the in-situ measurements, using in-line sensors monitoring each wafer. The sensor data is subjected to Statistical Quality Control (SQC) to determine if deviations from the required process observable values can be attributed to noise in the system or are due to a sustained anomalous behavior of the equipment. Once a change in equipment behavior is detected, the process/equipment models are adjusted to match the new state of the equipment. The updated models are used to run subsequent wafers until a new SQC failure is observed. The algorithms developed have been implemented and tested, and are currently being used to control the etching of wafers under standard manufacturing conditions. >

Equipment fault detection using spatial signatures

This paper describes a new methodology for equipment fault detection. The key features of this methodology are that it allows for the incorporation of spatial information and that it can be used to detect and diagnose equipment faults simultaneously. This methodology consists of constructing a virtual wafer surface from spatial data and using physically based spatial signature metrics to compare the virtual wafer surface to an established baseline process surface in order to detect equipment faults. Statistical distributional studies of the spatial signature metrics provide the justification of determining the significance of the spatial signature. Data collected from a rapid thermal chemical vapor deposition (RTCVD) process and from a plasma enhanced chemical vapor deposition (PECVD) process are used to illustrate the procedures. This method detected equipment faults for all 11 wafers that were subjected to induced equipment faults in the RTCVD process, and even diagnosed the type of equipment fault for 10 of these wafers. This method also detected 42 of 44 induced equipment faults in the PECVD process.

A monitor wafer based controller for semiconductor processes

A monitor wafer based controller is described. The controller can be applied to equipment with or without in-situ sensors. The controller incorporates a novel multivariable adaptation methodology for the feedback controller that employs a layered process/equipment model. The layered model consists of an intrinsic component that corresponds to the initial settings to outputs model and an extrinsic component that transforms the inputs and the outputs of the intrinsic model. The adaptation strategy tunes the extrinsic model only and thus the adaptation strategy is independent of the intrinsic model form. The controller determines whether the process and equipment have changed state by using model based SQC to compare product parameter measurements with the composite model predictions. If a change in state is deduced, a model tuner is activated which adapts the extrinsic model to reflect the new state. To adapt the model, a local experiment design technique is applied that perturbs the equipment settings. Finally, a stepwise optimization technique that permits the specification and utilization of user preference toward changing some process inputs over others is used for determining the new process recipe. We report the controllers application to the plasma enhanced chemical vapor deposition of silicon nitride (PECVD Nitride) process run on Applied Materials Precision Reactor (AMT 5000). The controller has been tested in two ways. First, single and multiple faults were introduced in the process equipment. Second, the controller performance was observed during an extended period of routine use. These evaluations indicate that the controller is able to detect process state change and to adjust the process recipe to keep the process on target. >

Method for semiconductor process optimization using functional representations of spatial variations and selectivity

The authors present a methodology for determining the optimal equipment settings for a processing step based on experiment designs and model-based optimization. The proposed method for semiconductor process optimization uses two-layered models. The first layer involves creating a spatial model-one for each film of interest-of the etch results. The second layer maps the coefficients of the spatial models to equipment settings. All this is done before any optimization scheme is employed. The process engineer then may optimize the etch process by maximizing coefficients which contribute to the desired maximum etch rate, while minimizing coefficients which contribute to nonuniformity. He also may minimize coefficients which represent undesired etches, and thus obtain etch selectivity. The results of a study of a plasma-assisted silicon nitride etch step are presented.<<ETX>>

Advanced process control of a CVD tungsten reactor

An advanced multivariable in-line process control system, which combines traditional statistical process control (SPC) with feedback control, has been applied to the CVD tungsten process on an Applied Materials reactor. The goal of the model-based controller is to compensate for shifts in the process and maintain the wafer-state responses on target. The controller employs measurements made on test wafers to track the process behavior. This is accomplished by using model-based SPC, which compares the measurements with predictions obtained from process models. The process models relate the equipment settings to the wafer-state responses of interest. For CVD tungsten, a physically-based modeling approach was employed based on the reaction rate for the H/sub 2/ reduction of WF/sub 6/. The Arrhenius relationship for the kinetic model was linearized so that empirical modeling techniques could be applied. Statistically valid models were derived for deposition rate, film stress, and bulk resistivity using stepwise least-squares regression. On detecting a statistically significant shift in the process, the controller calculates adjustments to the settings to bring the process responses back on target. To achieve this, two additional test wafers are processed at slightly different settings than the current recipe. This local experiment allows the models to be updated to reflect the current process state. The model updates are expressed as multiplicative or additive changes in the process inputs and a change in the model constant. This approach for adaptive control also provides a diagnostic capability regarding the cause of the process shift. The adapted models are used by an optimizer to compute new settings to bring the responses back to target. The optimizer is capable of incrementally entering controllables into the strategy, reflecting the degree to which the engineer desires to manipulate each setting. The capability of the controller to compensate for induced shifts in the CVD tungsten process is demonstrated. Targets for film bulk resistivity and deposition rate were maintained while satisfying constraints on film stress and WF/sub 6/ conversion efficiency. The ability of the controller to update process models during routine operation is also investigated. The tuned process models better predict the process behavior over time compared to the untuned models and lead to improved process capability.

A methodology for the top-down synthesis of semiconductor process flows

Increasing expense of developing microelectronic manufacturing technology threatens to slow the growth of the electronics industry. This paper describes the progress we have made in developing methodologies and techniques to reduce the cost of designing microelectronic manufacturing flows. Our approach is to partition the task of process flow design into a number of abstraction levels and provide mechanisms to translate between these levels. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels. The paper enumerates the abstraction levels we have identified so far, and describes the translation mechanisms for a class of process design tasks: modification of an existing flow in response to change in performance requirements. Finally, we briefly describe a design environment that incorporates these ideas.

Recent advances in process synthesis for semiconductor devices

Recently, work has been started on a new methodology, called process synthesis, that has the potential to revolutionize integrated circuit (IC) process design in the same way that ASIC and microelectronics manufacturing science and technology (MMST) revolutionized circuit design and factory operation. This paper provides an overview of process synthesis, discusses synthesis methodologies, potential roadblocks to execution of this strategy, and presents recent progress in developing this capability.

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

Pass transistor designs using pocket implant to improve manufacturability for 256 Mbit DRAM and beyond

Pass transistor designs for scaled 256 Mbit DRAM are studied in this paper. It is shown, for the first time, that a L/sub g/=0.25 /spl mu/m and t/sub ox/=85 /spl Aring/ transistor utilizing a pocket implant together with a light V/sub TN/ implant (pocket-with-V/sub TN/) can satisfy the stringent requirements of subthreshold leakage, diode leakage, V/sub T/ during charging, and a tolerance for L/sub g/ variation of 0.08 /spl mu/m for manufacturability. The success of the pocket-implant device in meeting the above design spec is due to the reduced V/sub T/ roll-off at shorter L/sub g/ and reduced body effect at longer L/sub g/ compared to those of a conventional device. An optimum range of substrate bias is determined to be -1.5 to -2 V. It is also shown that the pocket implant does not degrade the gate oxide integrity nor channel hot-electron reliability.<<ETX>>

Model-based equipment diagnosis

A versatile methodology is described in which equipment models have been incorporated into a single process diagnostic system for the PECVD of silicon nitride. The diagnosis system has been developed and tested with data collected using an Applied Materials Precision 5000 single wafer reactor. The parametric equipment diagnosis system provides the basis for optimal control of multiple process responses by the classification of potential sources of equipment faults without the assistance of in-situ sensor data. The basis for the diagnosis system is the use of tuned empirical equipment models which have been developed using a physically-based experimental design. Nine individual site-specific models were used to provide an effective method of modeling the spatially-dependent process variations across the wafer with better sensitivity than mean-based models. The diagnostic system has been tested using data that was produced by adjusting the actual equipment controls to artificially simulate a variety of possible subtle equipment drifts and shifts. Statistical algorithms have been implemented which detect equipment drift, shift and variance stability faults using the difference between the predicted process responses to the off-line measured process responses. Fault classification algorithms have been developed to classify the most likely causes for the process drifts and shifts using a pattern recognition system based upon flexible discriminant analysis.