Sharad Saxena

A monitor wafer based controller for semiconductor processes

A monitor wafer based controller is described. The controller can be applied to equipment with or without in-situ sensors. The controller incorporates a novel multivariable adaptation methodology for the feedback controller that employs a layered process/equipment model. The layered model consists of an intrinsic component that corresponds to the initial settings to outputs model and an extrinsic component that transforms the inputs and the outputs of the intrinsic model. The adaptation strategy tunes the extrinsic model only and thus the adaptation strategy is independent of the intrinsic model form. The controller determines whether the process and equipment have changed state by using model based SQC to compare product parameter measurements with the composite model predictions. If a change in state is deduced, a model tuner is activated which adapts the extrinsic model to reflect the new state. To adapt the model, a local experiment design technique is applied that perturbs the equipment settings. Finally, a stepwise optimization technique that permits the specification and utilization of user preference toward changing some process inputs over others is used for determining the new process recipe. We report the controllers application to the plasma enhanced chemical vapor deposition of silicon nitride (PECVD Nitride) process run on Applied Materials Precision Reactor (AMT 5000). The controller has been tested in two ways. First, single and multiple faults were introduced in the process equipment. Second, the controller performance was observed during an extended period of routine use. These evaluations indicate that the controller is able to detect process state change and to adjust the process recipe to keep the process on target. >

Advanced process control of a CVD tungsten reactor

An advanced multivariable in-line process control system, which combines traditional statistical process control (SPC) with feedback control, has been applied to the CVD tungsten process on an Applied Materials reactor. The goal of the model-based controller is to compensate for shifts in the process and maintain the wafer-state responses on target. The controller employs measurements made on test wafers to track the process behavior. This is accomplished by using model-based SPC, which compares the measurements with predictions obtained from process models. The process models relate the equipment settings to the wafer-state responses of interest. For CVD tungsten, a physically-based modeling approach was employed based on the reaction rate for the H/sub 2/ reduction of WF/sub 6/. The Arrhenius relationship for the kinetic model was linearized so that empirical modeling techniques could be applied. Statistically valid models were derived for deposition rate, film stress, and bulk resistivity using stepwise least-squares regression. On detecting a statistically significant shift in the process, the controller calculates adjustments to the settings to bring the process responses back on target. To achieve this, two additional test wafers are processed at slightly different settings than the current recipe. This local experiment allows the models to be updated to reflect the current process state. The model updates are expressed as multiplicative or additive changes in the process inputs and a change in the model constant. This approach for adaptive control also provides a diagnostic capability regarding the cause of the process shift. The adapted models are used by an optimizer to compute new settings to bring the responses back to target. The optimizer is capable of incrementally entering controllables into the strategy, reflecting the degree to which the engineer desires to manipulate each setting. The capability of the controller to compensate for induced shifts in the CVD tungsten process is demonstrated. Targets for film bulk resistivity and deposition rate were maintained while satisfying constraints on film stress and WF/sub 6/ conversion efficiency. The ability of the controller to update process models during routine operation is also investigated. The tuned process models better predict the process behavior over time compared to the untuned models and lead to improved process capability.

A methodology for the top-down synthesis of semiconductor process flows

Increasing expense of developing microelectronic manufacturing technology threatens to slow the growth of the electronics industry. This paper describes the progress we have made in developing methodologies and techniques to reduce the cost of designing microelectronic manufacturing flows. Our approach is to partition the task of process flow design into a number of abstraction levels and provide mechanisms to translate between these levels. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels. The paper enumerates the abstraction levels we have identified so far, and describes the translation mechanisms for a class of process design tasks: modification of an existing flow in response to change in performance requirements. Finally, we briefly describe a design environment that incorporates these ideas.

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

Fault isolation during semiconductor manufacturing using automated discovery from wafer tracking databases

Describes the use of automated discovery from databases for diagnosing the causes of misprocessing during semiconductor manufacturing. The database contains the history of the semiconductor wafers as they undergo various processing steps. A generate-and-test approach is taken for using such a database for automated diagnosis. Based on prior manual use of such databases, classes of queries to the database useful for fault isolation are identified. Patterns in the responses to these queries that are useful for fault isolation are also identified. Automated diagnosis is accomplished by automating query generation and the detection of potentially useful patterns. A prototype system was implemented and tested on a database from a wafer grinding and polishing facility. In addition to identifying previously known faults, the system also identified previously unknown faults.<<ETX>>

Diagnosis of semiconductor manufacturing equipment and processes

This paper describes part of the research performed during the Microelectronic Manufacturing Science and Technology (MMST) program on techniques for the diagnosis of equipment malfunctions and misprocessing during semiconductor manufacturing. The main motivation of this work was to investigate techniques for rapid diagnosis. Towards this goal, a number of equipment-level diagnosis techniques are described. These techniques use equipment models to diagnose equipment malfunctions at a given process step. The results obtained by applying these diagnosis approaches are very encouraging. The various approaches were able to diagnose a number of faults that were deliberately introduced to test the algorithms and the equipment faults that developed during the final demonstration of the MMST program. These techniques were applied to a TI-built Advanced Vacuum Processor (AVP) and an Applied Materials Precision reactor AMT 5000. >

Simultaneous control of multiple measures of nonuniformity using site models and monitor wafer control

Present day semiconductor manufacturing processes are subject to tight specifications. High yields with tight process specifications require drive to target process control. As the size of the wafer in the semiconductor industry increases, nonuniformity across the wafer becomes a crucial yield limiting issue. Modeling nonuniformity in terms of the equipment settings permits calculation of recipes required to achieve the desired nonuniformity. However, models for single measures of nonuniformity, such as standard deviation, or range, do not capture all aspects of the nonuniformity and often do not model well in terms of the equipment settings. This paper describes the use of spatial models to simultaneously quantify multiple measures of nonuniformity, and a controller to keep the nonuniformities within specifications, Use of spatial models in conjunction with a monitor wafer controller (MWC) enables the simultaneous control of multiple nonuniformity measures. The paper presents the results of applying the MWC with spatial models to a plasma enhanced TEOS (PETEOS) deposition process on an Applied Materials Precision 5000 (AMT5000). The controller has been keeping the PETEOS process within specifications for over two years.

Simultaneous control of multiple nonuniformity metrics using site models and monitor wafer control

Present day semiconductor manufacturing processes are subject to tight specifications. High yields with tight process specifications require proactive, drive to target, process control. As the size of the wafer in the semiconductor industry increases, nonuniformity across the wafer becomes a crucial yield limiting issue. Modeling nonuniformity in terms of the equipment settings permits calculation of recipes required to achieve the desired nonuniformity. Models for scaler metrics of nonuniformity, such as standard deviation, or range, do not capture all aspects of the nonuniformity (i.e., shape, symmetry, etc.). In this paper we describe the use of spatial models to quantify various measures of nonuniformity, and a controller to keep the nonuniformities within specifications. A flexible controller, called monitor wafer controller (MWC), has been reported previously for the control of semiconductor processes. Use of spatial models in conjunction with the MWC enables the simultaneous control of multiple nonuniformity metrics. The results of applying the MWC with spatial model to a Plasma Enhanced TEOS (PE-TEOS) deposition process on an Applied Materials Precision 5000 (AMT5000) reactor are presented. The controller has kept the interlevel-dielectric deposition process within specifications for over an year.

An application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOS

This paper describes a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology. The methodology consists of following the components: compact models for device performance and reliability, compact models for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications. This approach is illustrated by applying it to the design of CMOS gate shrinks from 0.35 /spl mu/m to 0.29 /spl mu/m drawn poly gate length. The synthesized devices were manufactured, meeting all performance and reliability requirements in the first silicon run.

Methods for the design of microelectronic devices and process flows for manufacturability

Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.