Joseph C. Davis

Physical oxide thickness extraction and verification using quantum mechanical simulation

Physical gate oxide thickness is extracted from TiN gate PMOS and NMOS capacitance voltage measurements using an efficient multi-band Hartree self-consistent Poisson solver. The extracted oxide thicknesses are then used to perform direct tunneling current simulations. Excellent agreement between measured a simulated tunnel current is obtained without the use of adjustable fitting parameters.

Equipment fault detection using spatial signatures

This paper describes a new methodology for equipment fault detection. The key features of this methodology are that it allows for the incorporation of spatial information and that it can be used to detect and diagnose equipment faults simultaneously. This methodology consists of constructing a virtual wafer surface from spatial data and using physically based spatial signature metrics to compare the virtual wafer surface to an established baseline process surface in order to detect equipment faults. Statistical distributional studies of the spatial signature metrics provide the justification of determining the significance of the spatial signature. Data collected from a rapid thermal chemical vapor deposition (RTCVD) process and from a plasma enhanced chemical vapor deposition (PECVD) process are used to illustrate the procedures. This method detected equipment faults for all 11 wafers that were subjected to induced equipment faults in the RTCVD process, and even diagnosed the type of equipment fault for 10 of these wafers. This method also detected 42 of 44 induced equipment faults in the PECVD process.

Achieving Uniformity in a Semiconductor Fabrication Process using Spatial Modeling

Abstract Material is deposited onto the wafer surface during several steps of wafer fabrication. This material must be deposited evenly across the entire wafer surface, close to the targeted thickness, and with little wafer-to-wafer variability. But unequal variances across the wafer and under different process conditions, as well as nonstationary correlation across a wafer, make these goals difficult to achieve, because traditional methods for optimizing deposition processes assume homogeneity and independence. We avoid these assumptions and determine the best settings of process variables using physically motivated statistical models for the mean response, unequal variances, and nonstationary spatial correlation structure. Data from a rapid thermal chemical vapor deposition process is used to illustrate the approach. A simulation exercise demonstrates the advantages of fitting flexible variance models and using appropriate performance measures.

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

Improved Within‐Wafer Uniformity Modeling Through the Use of Maximum‐Likelihood Estimation of the Mean and Covariance Surfaces

Modern statistical modeling techniques for characterizing the spatial response of a single-wafer, process are presented. These techniques overcome the limitations of the commonly used ordinary least squares estimation procedure and provide models for the expected value and variance of the response. In addition, a procedure for generating a model of the covariance structure which relates the various points on the wafer is presented. These methods are applied to the characterization of the rapid thermal chemical vapor deposition of polysilicon on top of a layer of silicon dioxide. The results of this study indicate that the simultaneous estimation of mean and variance models results in a significantly better representation of the data than the standard constant-variance estimation of a mean model.

A robust metric for measuring within-wafer uniformity

Within-wafer uniformity is traditionally measured by the signal-to-noise ratio (SNR), defined as the estimated standard-deviation of within-wafer measurements over the mean of those measurements, Unfortunately, in the presence of deterministic variations of the response over the wafer (such as the bulls eye effect of some processes), the SNR is sensitive to both the location and the number of the measurements taken, A robust metric for describing within-wafer uniformity is developed and compared with the SNR method. The new metric, termed the integration statistic (I) is shown to be robust to both the location and number of measurements taken on the wafer and has lower variance than the SNR metric. The implications of this robust behavior are that fewer measurements can be taken to achieve a given accuracy in the uniformity estimate and that uniformity estimates are consistent with respect to variations in the orientation of the uniformity pattern to the measurement pattern.

An application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOS

This paper describes a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology. The methodology consists of following the components: compact models for device performance and reliability, compact models for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications. This approach is illustrated by applying it to the design of CMOS gate shrinks from 0.35 /spl mu/m to 0.29 /spl mu/m drawn poly gate length. The synthesized devices were manufactured, meeting all performance and reliability requirements in the first silicon run.

Statistical aspects of tuning simulators to noisy data

The purpose of TCAD tools is to reduce the cost of developing new semiconductor technologies by replacing real wafers with simulations. If the process flows and device structures can be simulated accurately, then new device designs can be analyzed using simulations instead of real wafers. However, due to uncertainty in material coefficients and deficiencies in the physical models, process and device simulators often fail to provide the accuracy necessary for predictive device design, thereby limiting the impact of TCAD on device development cost. To address this problem, process and device simulators are often tuned to match experimental data, i.e. the simulator coefficients are adjusted such that the simulator outputs match experimentally measured data. However, the experimental data to which the simulators are tuned contain noise due to both process variation and measurement noise. Since tuning parameters are adjusted such that the simulator outputs, which are deterministic, match the experimental data, the uncertainty in the data implies uncertainty in the optimal values of the tuning parameters. This paper presents a methodology for tuning to uncertain and sparse experimental data and estimating the tuning parameter distribution based on the experimental data uncertainty. This distribution can be used to determine whether there is enough data to generate confidence in the optimal values of the tuned parameters. Additionally, we show how the tuned parameter distribution can be used to estimate the uncertainty in simulations conducted at conditions other than those used for tuning.

Methods for the design of microelectronic devices and process flows for manufacturability

Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.

Reducing silicon usage during technology development-a variance analysis approach

During the development of semiconductor process flows, various process and device design alternatives must be evaluated to allow identification of the best candidate flow. In a development fab, this comparison is made in the presence of inherent manufacturing variation together with the variation associated with changes such as aggressive lithographic scaling and adoption of new unit processes. In this environment of high process variability, it is difficult to identify the best performance recipe from a set of candidate recipes. The problem is further exacerbated by the need to minimize silicon usage to lower development costs. In this paper, we describe a method to enhance the ability to detect the impact of design alternatives on device performances. The method uses simple statistical concepts to first account for and then adjust for the various sources of variation. The approach has two advantages. First, it significantly reduces the amount of silicon required for recipe comparison. The method allows us to evaluate flows based on as little as half- or quarter-wafer allocation without compromising experimental resolution. Second, the approach decouples the problem of evaluating design alternatives for performance improvement from the problem of controlling the higher variation associated with new processes. Once a good candidate recipe has been identified with the proposed method, it may be transferred to a more expensive but tightly controlled fab for volume production.