Suraj Rao

Equipment fault detection using spatial signatures

This paper describes a new methodology for equipment fault detection. The key features of this methodology are that it allows for the incorporation of spatial information and that it can be used to detect and diagnose equipment faults simultaneously. This methodology consists of constructing a virtual wafer surface from spatial data and using physically based spatial signature metrics to compare the virtual wafer surface to an established baseline process surface in order to detect equipment faults. Statistical distributional studies of the spatial signature metrics provide the justification of determining the significance of the spatial signature. Data collected from a rapid thermal chemical vapor deposition (RTCVD) process and from a plasma enhanced chemical vapor deposition (PECVD) process are used to illustrate the procedures. This method detected equipment faults for all 11 wafers that were subjected to induced equipment faults in the RTCVD process, and even diagnosed the type of equipment fault for 10 of these wafers. This method also detected 42 of 44 induced equipment faults in the PECVD process.

Monitoring multistage integrated circuit fabrication processes

This paper presents a process monitoring system, which is designed to be used for monitoring VLSIC and other multistage manufacturing processes. The proposed process monitor can 1) simultaneously detect a variety of out-of-control conditions, 2) quantify the magnitude of process change, and 3) be used to compute the probability of meeting specifications. Average run length simulations show that for a single-stage process, the monitor is at least as good as the Shewhart-CUSUM charts for detecting changes in the distribution of the monitored characteristics. For a multistage process, however, the Bayesian monitor can significantly reduce the detection time by using in-line correlation information from earlier stages. The monitor has been applied to data from a state-of-the-art fabrication facility, and the results are promising.

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

Run-to-run process control of oxide CMP using integrated metrology

Process control of dielectric CMP has become more stringent as device dimensions decrease. This study reports on the improvement in process control that was obtained by using an integrated metrology tool, and automated, factory-level, process control algorithms. The control methodology was proven to be capable of handling multiple pattern levels, with different pattern densities, on multiple polishers in an advanced-prototype/development fab. The improvement in control and throughput with respect to offline metrology and manual control is presented.. Residual sources of variation are analyzed, and schema for further improvements in control capability are presented, based on tests conducted.

Statistical aspects of tuning simulators to noisy data

The purpose of TCAD tools is to reduce the cost of developing new semiconductor technologies by replacing real wafers with simulations. If the process flows and device structures can be simulated accurately, then new device designs can be analyzed using simulations instead of real wafers. However, due to uncertainty in material coefficients and deficiencies in the physical models, process and device simulators often fail to provide the accuracy necessary for predictive device design, thereby limiting the impact of TCAD on device development cost. To address this problem, process and device simulators are often tuned to match experimental data, i.e. the simulator coefficients are adjusted such that the simulator outputs match experimentally measured data. However, the experimental data to which the simulators are tuned contain noise due to both process variation and measurement noise. Since tuning parameters are adjusted such that the simulator outputs, which are deterministic, match the experimental data, the uncertainty in the data implies uncertainty in the optimal values of the tuning parameters. This paper presents a methodology for tuning to uncertain and sparse experimental data and estimating the tuning parameter distribution based on the experimental data uncertainty. This distribution can be used to determine whether there is enough data to generate confidence in the optimal values of the tuned parameters. Additionally, we show how the tuned parameter distribution can be used to estimate the uncertainty in simulations conducted at conditions other than those used for tuning.

Methods for the design of microelectronic devices and process flows for manufacturability

Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.

RF-on polysilicon etch defectivity monitor for manufacturing and process development

Decreasing gate length and increasing chip size are resulting in higher kill ratios from blocked edge defects at polysilicon gate etch. As a result etcher defectivity needs to be closely monitored and tightly controlled. In this work the usefulness of blanket etch-back of an poly-Si/SiO/sub 2//Si wafer to monitor the particle performance of the etcher is presented. This monitoring method predicts the particle impact on product wafers and offers information about the particle generation event. In this study two sources of defects were seen-Si/O etch by-product flakes and Al/O/F/Si particles. Applicability of this monitor to guide process improvement is discussed.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

In integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (R c ), and the gate sheet resistance (R s ); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (I d ) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as R c vs R s and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Reducing silicon usage during technology development-a variance analysis approach

During the development of semiconductor process flows, various process and device design alternatives must be evaluated to allow identification of the best candidate flow. In a development fab, this comparison is made in the presence of inherent manufacturing variation together with the variation associated with changes such as aggressive lithographic scaling and adoption of new unit processes. In this environment of high process variability, it is difficult to identify the best performance recipe from a set of candidate recipes. The problem is further exacerbated by the need to minimize silicon usage to lower development costs. In this paper, we describe a method to enhance the ability to detect the impact of design alternatives on device performances. The method uses simple statistical concepts to first account for and then adjust for the various sources of variation. The approach has two advantages. First, it significantly reduces the amount of silicon required for recipe comparison. The method allows us to evaluate flows based on as little as half- or quarter-wafer allocation without compromising experimental resolution. Second, the approach decouples the problem of evaluating design alternatives for performance improvement from the problem of controlling the higher variation associated with new processes. Once a good candidate recipe has been identified with the proposed method, it may be transferred to a more expensive but tightly controlled fab for volume production.

A model-based approach for process design and its application to the titanium salicide process

Process technology development constitutes a significant cost in manufacturing integrated circuits. In this paper, we present a model-based approach for developing new process technology rapidly and inexpensively, using the salicide process to demonstrate the concepts. This approach is applied to evaluate performance tradeoffs, to develop insight into the underlying process physics, to quantify the impact of the salicide process on the device and circuit performance, and to estimate the process variability. The key idea of this approach is to group a sequence of process steps into a process module, and build simple and accurate process models for the module. The paper also illustrates the use of this model-based approach in synthesizing optimal processes rapidly based on requirements, contributing to the reduction of technology development cost and cycle time.